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W27L010Q-12 PDF预览

W27L010Q-12

更新时间: 2024-11-08 19:51:47
品牌 Logo 应用领域
华邦 - WINBOND 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
16页 259K
描述
EEPROM, 128KX8, 120ns, Parallel, CMOS, PDSO32, 8 X 14 MM, STSOP1-32

W27L010Q-12 技术参数

生命周期:Obsolete零件包装代码:TSOP1
包装说明:TSOP1,针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.84
最长访问时间:120 nsJESD-30 代码:R-PDSO-G32
长度:12.4 mm内存密度:1048576 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL编程电压:12 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:8 mm
Base Number Matches:1

W27L010Q-12 数据手册

 浏览型号W27L010Q-12的Datasheet PDF文件第2页浏览型号W27L010Q-12的Datasheet PDF文件第3页浏览型号W27L010Q-12的Datasheet PDF文件第4页浏览型号W27L010Q-12的Datasheet PDF文件第5页浏览型号W27L010Q-12的Datasheet PDF文件第6页浏览型号W27L010Q-12的Datasheet PDF文件第7页 
W27L010  
´ 8 ELECTRICALLY ERASABLE EPROM  
128K  
GENERAL DESCRIPTION  
The W27L010 is a high speed, low power consumption Electrically Erasable and Programmable Read  
Only Memory organized as 131072 ´ 8 bits. It requires only one supply in the range of 3.0V to 3.6V in  
normal read mode. The W27L010 provides an electrical chip erase function.  
FEATURES  
· High speed access time:  
120/150 nS (max.)  
· +14V erase/+12V programming voltage  
· Fully static operation  
· Read operating current: 10 mA (max.)  
· All inputs and outputs directly TTL/CMOS  
· Erase/Programming operating current:  
compatible  
30 mA (max.)  
· Three-state outputs  
· Standby current: 20 mA (max.)  
· Available packages: 32-pin 600 mil DIP, 32-lead  
· Low voltage power supply range, 3.0V to 3.6V  
PLCC and STSOP  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
VDD  
#PGM  
NC  
Vpp  
A16  
A15  
A12  
A7  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
1
#PGM  
#CE  
Q0  
2
OUTPUT  
BUFFER  
.
CONTROL  
3
.
A14  
A13  
A8  
4
#OE  
Q7  
5
A6  
6
A5  
7
A9  
32-pin DIP  
A11  
A4  
8
A0  
A3  
9
#OE  
A10  
CORE  
ARRAY  
A2  
10  
11  
12  
13  
14  
.
.
DECODER  
A1  
#CE  
Q7  
A0  
A16  
Q0  
Q6  
Q5  
Q4  
Q3  
Q1  
Q2  
18  
17  
15  
16  
VDD  
VSS  
VPP  
Vss  
#
A
1
2
A
1
5
A
1
6
V
p
p
V
D
P
G
M
N
C
D
3
2
3
1
4
3
2
1
3
0
5
6
7
8
9
10  
11  
12  
13  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A14  
A13  
A8  
A9  
A11  
#OE  
A10  
#CE  
Q7  
A7  
A6  
PIN DESCRIPTION  
A5  
A4  
A3  
A2  
A1  
A0  
Q0  
32-pin PLCC  
SYMBOL  
DESCRIPTION  
Address Inputs  
Data Inputs/Outputs  
1
8
1
9
2
0
1
7
1
4
1
5
1
6
A0- A16  
Q0- Q7  
#CE  
Q
1
Q
2
V
s
s
Q
3
Q
4
Q
5
Q
6
A11  
A9  
A8  
A13  
A14  
NC  
1
2
3
4
5
6
7
#OE  
A10  
#CE  
Q7  
Q6  
Q5  
Q4  
Q3  
Vss  
Q2  
Q1  
Q0  
A0  
A1  
A2  
A3  
Chip Enable  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
#OE  
Output Enable  
Program Enable  
Program/Erase Supply Voltage  
Power Supply  
#PGM  
VPP  
#PGM  
VDD  
8
9
32-pin  
TSOP  
Vpp  
A16  
A15  
A12  
A7  
A6  
A5  
A4  
10  
11  
12  
13  
14  
15  
16  
VDD  
Vss  
Ground  
NC  
No Connection  
Publication Release Date: June 2001  
Revision A5  
- 1 -  

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