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W27L02P-70 PDF预览

W27L02P-70

更新时间: 2024-09-18 22:06:19
品牌 Logo 应用领域
华邦 - WINBOND 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
15页 354K
描述
256K X 8 ELECTRIC ALLY ERASABLE EPROM

W27L02P-70 技术参数

生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ, LDCC32,.5X.6针数:32
Reach Compliance Code:unknownECCN代码:3A991.B.1.B.1
HTS代码:8542.32.00.51风险等级:5.84
Is Samacsys:N最长访问时间:70 ns
命令用户界面:NO数据轮询:NO
JESD-30 代码:R-PQCC-J32长度:13.97 mm
内存密度:2097152 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:32字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX8封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL电源:3.3 V
编程电压:12 V认证状态:Not Qualified
座面最大高度:3.56 mm最大待机电流:0.00002 A
子类别:EEPROMs最大压摆率:0.03 mA
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD切换位:NO
宽度:11.43 mmBase Number Matches:1

W27L02P-70 数据手册

 浏览型号W27L02P-70的Datasheet PDF文件第2页浏览型号W27L02P-70的Datasheet PDF文件第3页浏览型号W27L02P-70的Datasheet PDF文件第4页浏览型号W27L02P-70的Datasheet PDF文件第5页浏览型号W27L02P-70的Datasheet PDF文件第6页浏览型号W27L02P-70的Datasheet PDF文件第7页 
W27L02  
256K × 8 ELECTRICALLY ERASABLE EPROM  
1. GENERAL DESCRIPTION  
The W27L02 is a high speed, low power consumption Electrically Erasable and Programmable Read  
Only Memory organized as 262,144 x 8 bits. It requires only one supply in the range of 3.3V ±10% in  
normal read mode. The W27L02 provides an electrical chip erase function.  
2. FEATURES  
+12V erase/programming voltage  
Fully static operation  
Wide range for power supply voltage:  
3.3V ±10%  
High speed access time: 70/90 nS (max.)  
Read operating current: 15 mA (max.)  
All inputs and outputs directly TTL/CMOS  
compatible  
Three-state outputs  
Erase/Programming operating current:  
30 mA (max.)  
Available packages: 32-lead PLCC and 32-lead  
STSOP  
Standby current: 20 µA (max.)  
3. PIN CONFIGURATIONS  
4. BLOCK DIAGRAM  
VDD  
Vss  
V
PP  
Q0  
.
#PGM  
#CE  
OUTPUT  
BUFFER  
CONTROL  
DECODER  
.
#
Q7  
#OE  
A
1
A
1
6
A
1
2
A
1
5
V
p
p
V
D
D
P
G
M 7  
3
2
3
4
3
2
1
3
1
0
A0  
.
5
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Q0  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A14  
A13  
6
CORE  
ARRAY  
7
A8  
8
A9  
32-lead PLCC  
9
A11  
#OE  
A10  
#CE  
Q7  
.
10  
11  
12  
13  
A17  
1
8
1
9
2
1
7
1
1
5
1
6
0
4
Q
1
Q
2
V
s
Q
3
Q
Q
5
Q
6
4
s
5. PIN DESCRIPTION  
1
2
3
4
5
6
7
8
32  
A11  
A9  
A8  
A13  
A14  
A17  
#PGM  
VDD  
VPP  
A16  
A15  
A12  
A7  
A6  
A5  
A4  
#OE  
A10  
#CE  
Q7  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
SYMBOL  
A1 A17  
Q0 Q7  
#CE  
DESCRIPTION  
Q6  
Address Inputs  
Q5  
Q4  
Q3  
32-lead STSOP  
Data Inputs/Outputs  
Chip Enable  
Output Enable  
Program Enable  
Program/Erase Supply Voltage  
Power Supply  
V
9
10  
SS  
Q2  
Q1  
Q0  
11  
12  
13  
14  
15  
16  
A0  
A1  
A2  
A3  
#OE  
#PGM  
VPP  
VDD  
Vss  
Ground  
NC  
No Connection  
Publication Release Date: February 20, 2003  
Revision A3  
- 1 -  

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