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W280HT PDF预览

W280HT

更新时间: 2024-11-22 19:42:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
11页 176K
描述
Processor Specific Clock Generator, 66MHz, CMOS, PDSO56, 0.300 INCH, SSOP-56

W280HT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.9
其他特性:ALSO REQUIRES 2.5V SUPPLYJESD-30 代码:R-PDSO-G56
JESD-609代码:e0长度:18.415 mm
湿度敏感等级:1端子数量:56
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:66 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
主时钟/晶体标称频率:14.318 MHz认证状态:Not Qualified
座面最大高度:2.794 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

W280HT 数据手册

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PRELIMINARY  
W280  
Spread Spectrum Frequency Timing Generator  
for Integrated CPU  
Features  
Benefits  
• Mixed 2.5V and 3.3V Operation  
— Integrated CY2219 (main clock)and CY2310 (SDRAM  
buffer) into a single chip  
Supports Intel® Timna processors with integrated graphics  
and memory controllers  
— Combined with W134S, W280 offers an optimized and  
cost-reduced solution for Timna platform.  
• Multiple output clocks at different frequencies  
— Three CPU clocks at 66 MHz  
Single-chip main motherboard clock generator  
— Support for CPU and chipset  
— Eight PCI clocks at 33 MHz, 1 free-running  
— One DRCG reference clock at 66 MHz  
— Two synchronous APIC clocks at 33.3 MHz  
— One 3.3V and one 2.5V clock at 48 MHz  
— Two reference clocks at 14.318 MHz  
— Nine SDRAM output clocks  
— Support for multiple PCI slots and chipset  
— Drives one main memory clock generator, including  
DRCG (W134S)  
— Supports USB frequencies and I/O chip  
• Non-linear Spread Spectrum implementation  
• Two Frequency Select inputs  
• Low-Skew and Low-Jitter outputs  
• OE and Test Mode support  
Maximize EMI reduction  
Provides different operating modes for different applications  
Meet tight system timing requirements at high frequency  
Enables ATE and “bed of nails” testing  
• 56-pin SSOP package  
Widely available, standard package enables lower cost  
[1]  
Pin Configuration  
56  
55  
54  
53  
52  
51  
50  
49  
48  
DD_APIC  
Note:  
1. Pins denoted by * have internal pull-up resistor. Designer  
should not solely rely on internal resistor to set I/O pins  
HIGH.  
Intel and Pentium are registered trademarks of Intel Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
August 4, 2000, rev. *A  

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