W281
PRELIMINARY
Spread Spectrum Frequency Timing Generator
for Integrated CPU
Features
Benefits
• Mixed 2.5V and 3.3V operation
— IntegratedCY2219(mainClock)andCY2310(SDRAM
buffer) into a single chip
Supports Intel Timna processors with integrated graphics and
memory controllers
— Combined with W134S, W281 offers an optimized and
cost reduced solution for Timna platform
• Multiple output clocks at different frequencies
— Two CPU clocks at 66 MHz
Single-chip main motherboard clock generator
— Support for CPU and chipset
— Six PCI clocks at 33 MHz, 1 free-running
— One DRCG reference clock at 66 MHz or 50 MHz
— One synchronous APIC clock at 16.67 MHz
— One 3.3V and one 2.5V clock at 48 MHz
— Two reference clocks at 14.318 MHz
— Nine SDRAM output clocks
— Support for multiple PCI slots and chipset
— Drives one main memory clock generator, including
DRCG (W134S)
— Supports USB frequencies and I/O chip
• Non-linear Spread Spectrum implementation
• Two Frequency Select inputs
• Low-skew and low-jitter outputs
• OE and Test Mode support
Maximize EMI reduction
Supports up to four CPU clock frequencies
Meets tight system timing requirements at high frequency
Enables ATE and “bed of nails” testing
• 48-pin SSOP package
Widely available, standard package enables lower cost
Pin Configuration[1]
Logic Block Diagram
SSOP
Top View
VDD_2V48M
APIC0
48
2V48M
3V48M
1
2
3
4
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VDD_APIC
VDD_CPU
VDD_3V48M
GND_48M
REF [0–1]
CPU0
XIN
5
6
MREF66_50
CPU0
CPU1_ICH
XOUT
GND_CPU
GND_REF
REF0
7
MREF66_50
VDD_MREF
GND_MREF
SDRAM_MTH
8
REF1
9
VDD_REF
CPU1_ICH
10
11
XIN
14.318
MHz
OSC.
Divider, Stop,
&Other
CPU
PLL
PCI0
PCI1
XOUT
Logic
PCI [0–5] (33.33 MHz)
APIC0 (16.67 MHz)
SDRAM0
12
13
VDD_SDRAM
GND_SDRAM
SDRAM1
GND_PCI
VDD_PCI
PCI2
14
15
16
17
18
SDATA
SDRAM2
PCI3
SDRAM_MTH
SDRAM [0-7]
SCLK
SDRAM3
PCI4
PCI5
VDD_SDRAM
GND_SDRAM
SDRAM_IN
30
29
SCLK
19
20
21
22
23
24
SYS
PLL
VDD_CORE
GND_CORE
SDATA
SDRAM4
SDRAM5
3V48M (48 MHz)
2V48M(48 MHz)
28
27
26
VDD_SDRAM
GND_SDRAM
SDRAM6
SDRAM_IN
SDRAM7
25
Note:
1. Pins denoted by * have internal pull-up resis-
tor. Designer should not solely rely on internal
resistor to set I/O pins HIGH,
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 31, 2000, rev. **