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W27L010S-90 PDF预览

W27L010S-90

更新时间: 2024-11-09 22:35:43
品牌 Logo 应用领域
华邦 - WINBOND 存储内存集成电路光电二极管输出元件输入元件可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 122K
描述
128K ⅴ 8 ELECTRICALLY ERASABLE EPROM

W27L010S-90 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP32,.56
针数:32Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.92最长访问时间:90 ns
其他特性:TTL/CMOS COMPATIBLE INPUT & OUTPUT命令用户界面:NO
数据轮询:NOJESD-30 代码:R-PDSO-G32
JESD-609代码:e0长度:20.45 mm
内存密度:1048576 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP32,.56
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V编程电压:12 V
认证状态:Not Qualified座面最大高度:3 mm
最大待机电流:0.00002 A子类别:EEPROMs
最大压摆率:0.01 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
切换位:NO宽度:11.3 mm
Base Number Matches:1

W27L010S-90 数据手册

 浏览型号W27L010S-90的Datasheet PDF文件第2页浏览型号W27L010S-90的Datasheet PDF文件第3页浏览型号W27L010S-90的Datasheet PDF文件第4页浏览型号W27L010S-90的Datasheet PDF文件第5页浏览型号W27L010S-90的Datasheet PDF文件第6页浏览型号W27L010S-90的Datasheet PDF文件第7页 
Preliminary W27L010  
128K ´ 8 ELECTRICALLY ERASABLE EPROM  
GENERAL DESCRIPTION  
The W27L010 is a high speed, low power consumption Electrically Erasable and Programmable Read  
Only Memory organized as 131072 ´ 8 bits. It requires only one supply in the range of 3.0V to 3.6V in  
normal read mode. The W27L010 provides an electrical chip erase function.  
FEATURES  
· High speed access time:  
90/120 nS (max.)  
· +14V erase/+12V programming voltage  
· Fully static operation  
· Read operating current: 10 mA (max.)  
· All inputs and outputs directly TTL/CMOS  
· Erase/Programming operating current:  
compatible  
30 mA (max.)  
· Three-state outputs  
· Standby current: 20 mA (max.)  
· Available packages: 32-pin 600 mil DIP, 450  
· Low voltage power supply range, 3.0V to 3.6V  
mil SOP and PLCC  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
Q0  
.
.
PGM  
CE  
OUTPUT  
BUFFER  
Vcc  
Vpp  
A16  
A15  
A12  
A7  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
1
CONTROL  
DECODER  
PGM  
NC  
2
Q7  
OE  
3
A14  
A13  
A8  
4
5
A0  
.
A6  
6
CORE  
ARRAY  
A5  
7
A9  
32-pin DIP  
A11  
A4  
8
.
A3  
9
OE  
A16  
A2  
10  
11  
12  
13  
14  
A10  
A1  
CE  
Q7  
V
CC  
A0  
GND  
Q0  
Q6  
Q5  
V
PP  
Q1  
Q2  
18  
17  
Q4  
Q3  
15  
16  
GND  
PIN DESCRIPTION  
/
A
1
6
A
A
1
5
V
p
p
V
c
P
SYMBOL  
DESCRIPTION  
Address Inputs  
Data Inputs/Outputs  
1
2
N
C
G
M
c
A0- A16  
Q0- Q7  
CE  
3
2
3
1
4
3
2
1
3
0
5
6
7
8
9
10  
11  
12  
13  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Q0  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A14  
A13  
A8  
Chip Enable  
A9  
Output Enable  
Program Enable  
Program/Erase Supply Voltage  
Power Supply  
Ground  
No Connection  
OE  
32-pin PLCC  
A11  
OE  
A10  
CE  
Q7  
PGM  
VPP  
1
8
1
9
2
0
1
7
1
4
1
5
1
6
VCC  
GND  
NC  
Q
1
Q
2
Q
5
G
N
D
Q
3
Q
4
Q
6
Publication Release Date: February 1999  
Revision A1  
- 1 -  

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