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W27LE520W-70* PDF预览

W27LE520W-70*

更新时间: 2024-11-08 03:09:15
品牌 Logo 应用领域
华邦 - WINBOND 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
16页 104K
描述
64K X 8 ELECTRICALLY ERASABLE EPROM

W27LE520W-70* 数据手册

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Advance Information W27LE520  
64K ´ 8 ELECTRICALLY ERASABLE EPROM  
GENERAL DESCRIPTION  
The W27LE520 is a high speed, low power Electrically Erasable and Programmable Read Only  
Memory organized as 65,536 ´ 8 bits. It includes latches for the lower 8 address lines to multiplex  
with the 8 data lines. To cooperate with the MCU, this device could save the external TTL  
component, also cost and space. It requires only one supply in the range of 3.0V to 3.6V or 4.5V to  
5.5V in normal read mode. The W27LE520 provides an electrical chip erase function. It will be a  
great convenient when you need to change/update the contents in the device.  
FEATURES  
· High Reliability CMOS Technology  
- 2K V ESD Protection  
- 200 mA Latchup Immunity  
· High speed access time: 70/90 nS (max.)  
· Read operating current: 8 mA/20 mA (max.)  
· Erase/Programming operating current  
· Fully static operation  
· All inputs and outputs directly LVTTL/CMOS  
compatible  
· Three-state outputs  
· Available packages: 20-pin TSSOP and 20-pin  
SOP  
30 mA (max.)  
· Standby current: 20 mA /100 mA (max.)  
· Unregulated battery power supply range,  
3.0V to 3.6V or 4.5V to 5.5V  
· +13V erase and programming voltage  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
1
2
3
4
5
6
7
8
9
10  
A10  
A12  
A14  
ALE  
A8  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
ALE  
OE / V  
OUTPUT  
BUFFER  
CONTROL  
AD1  
AD3  
AD5  
AD7  
GND  
PP  
L
V
DD  
TSSOP  
Top View  
A
T
C
H
E
S
AD7 - AD0  
OE/VPP  
A15  
MEMORY  
ARRAY  
DECODER  
AD6  
AD4  
AD2  
AD0  
A13  
A15 - A8  
A11  
A9  
V
DD  
GND  
1
VDD  
ALE  
A14  
A12  
A10  
A8  
20  
19  
18  
17  
OE/VPP  
A15  
2
PIN DESCRIPTION  
3
A13  
A11  
A9  
4
SYMBOL  
DESCRIPTION  
5
SOP  
Top View  
16  
15  
14  
13  
12  
11  
Address/Data Inputs/Outputs  
Address Inputs  
AD0- AD7  
A8- A15  
ALE  
6
AD0  
7
AD1  
AD2  
AD4  
Address Latch Enable  
8
AD3  
AD5  
AD7  
Output Enable, Program/Erase  
Supply Voltage  
OE/VPP  
9
AD6  
10  
GND  
VDD  
Power Supply  
Ground  
GND  
Publication Release Date: 4/26/2000  
Revision A1  
- 1 -  

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