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SY100S325JC PDF预览

SY100S325JC

更新时间: 2024-11-10 22:36:11
品牌 Logo 应用领域
麦瑞 - MICREL 转换器电平转换器驱动程序和接口锁存器接口集成电路
页数 文件大小 规格书
5页 103K
描述
LOW-POWER HEX ECL-to-TTL TRANSLATOR

SY100S325JC 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.47Is Samacsys:N
最大延迟:3.7 ns接口集成电路类型:ECL TO TTL TRANSLATOR
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.48 mm湿度敏感等级:1
位数:1功能数量:6
端子数量:28最高工作温度:85 °C
最低工作温度:输出锁存器或寄存器:NONE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):240电源:5,-4.5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Level Translators最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:11.48 mmBase Number Matches:1

SY100S325JC 数据手册

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LOW-POWER HEX  
ECL-to-TTL  
SY100S325  
TRANSLATOR  
DESCRIPTION  
FEATURES  
Max. propagation delay of 3.7ns  
IEE min. of –37mA  
The SY100S325 are hex translators for converting  
100K ECL logic levels to TTL logic levels. Inputs can be  
used as inverting, non-inverting or differential receivers.  
An internal reference voltage generator provides VBB for  
single-ended operation or for use in Schmitt trigger  
applications. All inputs have 75Kpull-down resistors.  
The outputs will go LOW when the inputs are either open  
or have the same potential.  
When used in single-ended operation, the apparent  
input threshold of the true inputs is 20mV to 40mV higher  
(positive) than the threshold of the complementary inputs.  
The VTTL and VEE power may be applied in either order.  
TTL outputs  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
25% faster than National's 325  
Differential inputs with built-in offset  
Voltage and temperature compensation for improved  
noise immunity  
VBB output for single-ended use  
Internal 75Kinput pull-down resistors  
Function and pinout compatible with Fairchild F100K  
PIN CONFIGURATIONS  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
25  
24 23 22 21 20 19  
V
TTL  
TTL  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
D
D
D
4
3
3
V
V
CC  
CC  
CC  
Top View  
PLCC  
J28-1  
V
V
V
V
EES  
BLOCK DIAGRAM  
V
2
EE  
Q
2
1
3
BB  
Q
4
D
2
V
BB  
5
6
7
8
9
10 11  
D
D
0
0
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
24 23 22 21 20 19  
D
D
D
4
1
18  
17  
16  
D
D
2
1
D
D
1
1
5
5
2
3
D
1
Top View  
Flatpack  
F24-1  
D
D
2
2
Q
Q
Q
5
4
3
4
5
6
15  
14  
13  
D0  
D0  
Q0  
D
D
3
3
7
8
9
10 11 12  
D
D
4
4
D
D
5
5
PIN NAMES  
Pin  
D0–D5  
D0–D5  
Q0–Q5  
VEES  
Function  
Data Inputs  
Inverting Data Inputs  
Data Outputs  
VEE Substrate  
VTTL  
TTL VCC Power Supply  
VCCO for ECL Outputs  
VCCA  
Rev.: F  
Amendment:/0  
Issue Date: July, 1999  
1

SY100S325JC 替代型号

型号 品牌 替代类型 描述 数据表
SY100S325JC MICROCHIP

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100325QI FAIRCHILD

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Low Power Hex ECL-to-TTL Translator

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