SY100S331
Micrel, Inc.
TRIPLE D
FLIP-FLOP
SY100S331
FEATURES
DESCRIPTION
TheSY100S331offersthreeD-type,edge-triggeredmaster/
slave flip-flops with true and complement outputs, designed
for use in high-performance ECL systems. Each flip-flop is
controlled by a common clock (CPc), as well as its own clock
pulse (CPn). The resultant clock signal controlling the flip-flop
is the logical OR operation of these two clock signals. Data
entersthemasterwhenbothCPc andCPn areLOWandenters
the slave on the rising edge of either CPc or CPn (or both).
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SDn) and Direct Clear (CDn) signals. The MR, MS,
SDn and DCn signals override the clock signals. The inputs
on this device have 75kΩ pull-down resistors.
■ꢀ Max.ꢀtoggleꢀfrequencyꢀofꢀ800MHz
■ꢀ Differentialꢀoutputs
■ꢀ IEEꢀmin.ꢀofꢀ–80mA
■ꢀ Industryꢀstandardꢀ100KꢀECLꢀlevels
■ꢀ Extendedꢀsupplyꢀvoltageꢀoption:
VEEꢀ=ꢀ–4.2Vꢀtoꢀ–5.5V
■ꢀ Voltageꢀandꢀtemperatureꢀcompensationꢀforꢀimprovedꢀ
noiseꢀimmunity
■ꢀ Internalꢀ75kΩꢀinputꢀpull-downꢀresistors
■ꢀ 150%ꢀfasterꢀthanꢀFairchild
■ꢀ 40%ꢀlowerꢀpowerꢀthanꢀFairchild
■ꢀ FunctionꢀandꢀpinoutꢀcompatibleꢀwithꢀFairchildꢀF100K
■ꢀ Availableꢀinꢀ28-pinꢀPLCCꢀpackage
BLOCKꢀDIAGRAM
PINꢀNAMES
Pinꢀ
CP0 – CP2
CPc
Function
Individual Clock Inputs
Common Clock Input
Data Inputs
D0 – D2
CD0 – CD2
SDn
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
MR
MS
Q0 – Q2
Q0 – Q2
VEES
Data Outputs
Complementary Data Outputs
VEE Substrate
VCCA
VCCO for ECL Outputs
Rev.: I
Amendment: /0
M9999-060910
hbwhelp@micrel.com or (408) 955-1690
1
Issue Date: June 2010