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SY100S341JC PDF预览

SY100S341JC

更新时间: 2024-11-10 22:15:11
品牌 Logo 应用领域
麦瑞 - MICREL 移位寄存器
页数 文件大小 规格书
7页 116K
描述
8-BIT SHIFT REGISTER

SY100S341JC 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.48
计数方向:BIDIRECTIONAL系列:100S
JESD-30 代码:S-PQCC-J28JESD-609代码:e0
长度:11.48 mm逻辑集成电路类型:PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup:600000000 Hz湿度敏感等级:1
位数:8功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):240电源:-4.2/-5.5 V
传播延迟(tpd):1.2 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Shift Registers
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:11.48 mm
最小 fmax:600 MHz

SY100S341JC 数据手册

 浏览型号SY100S341JC的Datasheet PDF文件第2页浏览型号SY100S341JC的Datasheet PDF文件第3页浏览型号SY100S341JC的Datasheet PDF文件第4页浏览型号SY100S341JC的Datasheet PDF文件第5页浏览型号SY100S341JC的Datasheet PDF文件第6页浏览型号SY100S341JC的Datasheet PDF文件第7页 
8-BIT SHIFT  
REGISTER  
SY100S341  
FEATURES  
DESCRIPTION  
The SY100S341 offer eight D-type, edge-triggered flip-  
flops with both individual inputs for parallel operation as  
well as serial inputs for bidirectional shifting, and are  
designed for use in high-performance ECL systems. Data  
is clocked into the flip-flops on the rising edge of the clock.  
The mode of operation is selected by two Select inputs  
(S0, S1) which determine if the device performs a shift, hold  
or parallel entry function, as described in the Truth Table.  
The inputs on these devices have 75Kpull-down resistors.  
Max. shift frequency of 600MHz  
Max. Clock to Q delay of 1200ps  
IEE min. of –150mA  
Industry standard 100K ECL levels  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for improved  
noise immunity  
Internal 75Kinput pull-down resistors  
70% faster than Fairchild 300K at lower power  
Function and pinout compatible with Fairchild F100K  
PIN CONFIGURATIONS  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
11 10 9  
8 7 6 5  
12  
13  
14  
15  
16  
17  
18  
4
3
P4  
CP  
Q5  
Q4  
2
VEE  
VEES  
S0  
VCCA  
VCC  
VCC  
Q3  
Top View  
PLCC  
PIN NAMES  
1
J28-1  
28  
27  
26  
S1  
Label  
CP  
Function  
Clock Pulse Input  
P3  
Q2  
19 20 21 22 23 24 25  
S0 — S1  
D0 — D7  
P0 — P7  
Q0 — Q7  
VEES  
Select Inputs  
Serial Inputs  
Parallel Inputs  
Data Outputs  
24 23 22 21 20 19  
1
2
3
4
5
6
18  
P
P
2
1
P
P
P
5
6
7
17  
16  
15  
14  
13  
VEE Substrate  
VCCO for ECL Outputs  
Top View  
Flatpack  
F24-1  
P
0
0
VCCA  
D
D
7
Q
0
Q
Q
7
8
Q
1
7
8
9 10 11 12  
Rev.: G  
Amendment:/0  
Issue Date: July, 1999  
1

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