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SY100S336_06 PDF预览

SY100S336_06

更新时间: 2024-11-11 05:04:27
品牌 Logo 应用领域
麦瑞 - MICREL 移位寄存器计数器
页数 文件大小 规格书
10页 126K
描述
4-STAGE COUNTER/SHIFT REGISTER

SY100S336_06 数据手册

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SY100S336  
4-STAGE COUNTER/  
SHIFT REGISTER  
FEATURES  
DESCRIPTION  
The SY100S336 functions either as a modulo-16 up/  
down counter or as a 4-bit bidirectional shift register and is  
designed for use in high-performance ECL systems. Three  
Select inputs (Sn) are provided for determining the mode of  
operation. The Function Table lists the available modes of  
operation. In order to allow cascading for multistage  
counters, two Count Enable controls (CEP, CET) are  
provided. The CET input also functions as the Serial Data  
input (S0) for a shift-up operation, while the D3 input serves  
as the Serial Data input for the shift-down operation.  
When the device is in the counting mode, the Terminal  
Count (TC) goes to a logical LOW when the count reaches  
15 for count-up or reaches 0 for count-down. When in the  
shift mode, the TC output simply repeats the Q3 output.  
The flexiblity provided by the TC/Q3 output and the D0/  
CET input allows these signals to be interconnected from  
one stage to the next higher stage for multistage counting  
or shift-up operations. The individual Presets (Pn) allow  
initialization of the counter by entering data in parallel to  
preset the counter. A logic HIGH on the Master Reset (MR)  
overrides all other inputs and asynchronously clears the  
flip-flops. An additional synchronous Clear is provided, as  
well as a complement function which synchronously inverts  
the contents of the flip-flops. All inputs have 75Kpull-  
down resistors.  
Max. shift frequency of 700MHz  
Clock to Q delay max. of 1100ps  
IEE min. of –170mA  
Internal 75Kinput pull-down resistors  
Industry standard 100K ECL levels  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for improved  
noise immunity  
50% faster than Fairchild 300K at lower power  
Function and pinout compatible with Fairchild F100K  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
PIN NAMES  
Pin  
Function  
Clock Pulse Input  
CP  
CEP  
Count Enable Parallel Input (Active LOW)  
D0/CET  
Serial Data Input/Count Enable Trickle  
Input (Active LOW)  
S0 — S2  
MR  
Select Inputs  
Master Reset Input  
VEE Substrate  
VEES  
VCCA  
VCCO for ECL Outputs  
Preset Inputs  
P0 – P3  
D3  
Serial Data Input  
Terminal Count Output  
Data Outputs  
TC  
Q0 — Q3  
Q0 — Q3  
Complementary Data Outputs  
Rev.: H  
Amendment:/0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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