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SY100S336AJZ PDF预览

SY100S336AJZ

更新时间: 2024-11-11 05:04:27
品牌 Logo 应用领域
麦瑞 - MICREL 移位寄存器计数器
页数 文件大小 规格书
10页 126K
描述
ENHANCED 4-STAGE COUNTER/SHIFT REGISTER

SY100S336AJZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCJ, LDCC28,.5SQ
针数:28Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.66
其他特性:CAN BE USED AS 4-BIT BIDIRECTIONAL SHIFT REGISTER计数方向:BIDIRECTIONAL
系列:100SJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:SYNCHRONOUS湿度敏感等级:2
位数:4功能数量:1
端子数量:28最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:-4.5 V
传播延迟(tpd):1.1 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Counters
表面贴装:YES技术:ECL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:11.48 mm
最小 fmax:700 MHzBase Number Matches:1

SY100S336AJZ 数据手册

 浏览型号SY100S336AJZ的Datasheet PDF文件第2页浏览型号SY100S336AJZ的Datasheet PDF文件第3页浏览型号SY100S336AJZ的Datasheet PDF文件第4页浏览型号SY100S336AJZ的Datasheet PDF文件第5页浏览型号SY100S336AJZ的Datasheet PDF文件第6页浏览型号SY100S336AJZ的Datasheet PDF文件第7页 
SY100S336A  
ENHANCED 4-STAGE  
COUNTER/SHIFT REGISTER  
DESCRIPTION  
FEATURES  
Max. shift frequency of 700MHz  
Clock to Q delay max. of 1100ps  
Sn to TC speed improved by 50%  
Sn set-up and hold time reduced by more than 50%  
IEE min. of –170mA  
The SY100S336A is functionally the same as the  
SY100S336, but has Sn to TC speed and Sn set-up and  
hold times significantly improved, allowing for higher clock  
frequency when used as a cascaded multi-stage counter.  
The SY100S336A functions either as a modulo-16 up/  
down counter or as a 4-bit bidirectional shift register and is  
designed for use in high-performance ECL systems. Three  
Select inputs (Sn) are provided for determining the mode of  
operation. The Function Table lists the available modes of  
operation. In order to allow cascading for multistage  
counters, two Count Enable controls (CEP, CET) are  
Industry standard 100K ECL levels  
Internal 75Kinput pull-down resistors  
Extended supply voltage option:  
VEE = –4.2V to –5.5V  
Voltage and temperature compensation for improved provided. The CET input also functions as the Serial Data  
noise immunity  
input (S0) for a shift-up operation, while the D3 input serves  
as the Serial Data input for the shift-down operation.  
When the device is in the counting mode, the Terminal  
Count (TC) goes to a logical LOW when the count reaches  
15 for count-up or reaches 0 for count-down. When in the  
shift mode, the TC output simply repeats the Q3 output.  
The flexiblity provided by the TC/Q3 output and the D0/  
CET input allows these signals to be interconnected from  
one stage to the next higher stage for multistage counting  
or shift-up operations. The individual Presets (Pn) allow  
initialization of the counter by entering data in parallel to  
preset the counter. A logic HIGH on the Master Reset (MR)  
overrides all other inputs and asynchronously clears the  
flip-flops. An additional synchronous Clear is provided, as  
well as a complement function which synchronously inverts  
the contents of the flip-flops. All inputs have 75Kpull-  
down resistors.  
50% faster than Fairchild 300K at lower power  
Function and pinout compatible with Fairchild F100K  
Available in 24-pin CERPACK and 28-pin PLCC  
packages  
PIN NAMES  
Pin  
Function  
Clock Pulse Input  
CP  
CEP  
Count Enable Parallel Input (Active LOW)  
D0/CET  
Serial Data Input/Count Enable Trickle  
Input (Active LOW)  
S0 — S2  
MR  
Select Inputs  
Master Reset Input  
VEE Substrate  
VEES  
VCCA  
VCCO for ECL Outputs  
Preset Inputs  
P0 – P3  
D3  
Serial Data Input  
Terminal Count Output  
Data Outputs  
TC  
Q0 — Q3  
Q0 — Q3  
Complementary Data Outputs  
Rev.: H  
Amendment:/0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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