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SY100S336AJC PDF预览

SY100S336AJC

更新时间： 2024-11-10 22:59:23
品牌 Logo 应用领域
麦瑞 - MICREL 移位寄存器计数器触发器逻辑集成电路
页数 文件大小 规格书
9页 152K
描述
ENHANCED 4-STAGE COUNTER/SHIFT REGISTER

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中文翻译

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SY100S336AJC 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：PLASTIC, LCC-28Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.74
Is Samacsys：N其他特性：CAN BE USED AS 4-BIT BIDIRECTIONAL SHIFT REGISTER
计数方向：BIDIRECTIONAL系列：100S
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：
输出特性：OPEN-EMITTER封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
电源：-4.5 V最大电源电流（ICC）：170 mA
传播延迟（tpd）：1.1 ns认证状态：Not Qualified
子类别：Counters表面贴装：YES
技术：ECL温度等级：OTHER
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
触发器类型：POSITIVE EDGE最小 fmax：700 MHz
Base Number Matches：1

SY100S336AJC 数据手册

 浏览型号SY100S336AJC的Datasheet PDF文件第2页浏览型号SY100S336AJC的Datasheet PDF文件第3页浏览型号SY100S336AJC的Datasheet PDF文件第4页浏览型号SY100S336AJC的Datasheet PDF文件第5页浏览型号SY100S336AJC的Datasheet PDF文件第6页浏览型号SY100S336AJC的Datasheet PDF文件第7页 
ENHANCED 4-STAGE  
COUNTER/SHIFT REGISTER  
SY100S336A  
FEATURES  
DESCRIPTION  
ꢀ Max. shift frequency of 700MHz  
ꢀ Clock to Q delay max. of 1100ps  
ꢀ Sn to TC speed improved by 50%  
ꢀ Sn set-up and hold time reduced by more than 50%  
ꢀ IEE min. of –170mA  
The SY100S336A is functionally the same as the  
SY100S336, but has Sn to TC speed and Sn set-up and  
hold times significantly improved, allowing for higher clock  
frequency when used as a cascaded multi-stage counter.  
The SY100S336A functions either as a modulo-16 up/  
down counter or as a 4-bit bidirectional shift register and is  
designed for use in high-performance ECL systems. Three  
Select inputs (Sn) are provided for determining the mode of  
operation. The Function Table lists the available modes of  
operation. In order to allow cascading for multistage  
counters, two Count Enable controls (CEP, CET) are  
ꢀ Industry standard 100K ECL levels  
ꢀ Internal 75KΩ input pull-down resistors  
ꢀ Extended supply voltage option:  
VEE = –4.2V to –5.5V  
ꢀ Voltage and temperature compensation for improved provided. The CET input also functions as the Serial Data  
noise immunity  
input (S0) for a shift-up operation, while the D3 input serves  
as the Serial Data input for the shift-down operation.  
When the device is in the counting mode, the Terminal  
Count (TC) goes to a logical LOW when the count reaches  
15 for count-up or reaches 0 for count-down. When in the  
shift mode, the TC output simply repeats the Q3 output.  
The flexiblity provided by the TC/Q3 output and the D0/  
CET input allows these signals to be interconnected from  
one stage to the next higher stage for multistage counting  
or shift-up operations. The individual Presets (Pn) allow  
initialization of the counter by entering data in parallel to  
preset the counter. A logic HIGH on the Master Reset (MR)  
overrides all other inputs and asynchronously clears the  
flip-flops. An additional synchronous Clear is provided, as  
well as a complement function which synchronously inverts  
the contents of the flip-flops. All inputs have 75KΩ pull-  
down resistors.  
ꢀ 50% faster than Fairchild 300K at lower power  
ꢀ Function and pinout compatible with Fairchild F100K  
ꢀ Available in 24-pin CERPACK and 28-pin PLCC  
packages  
PIN CONFIGURATIONS  
11 10 9  
8 7 6 5  
P
0
12  
13  
14  
15  
16  
17  
18  
4
3
Q
Q
2
2
CP  
VEE  
2
V
V
V
CCA  
Top View  
PLCC  
J28-1  
V
EES  
1
CC  
MR  
28  
27  
26  
CC  
PIN NAMES  
S
0
1
Q
Q
1
1
S
19 20 21 22 23 24 25  
Pin  
Function  
Clock Pulse Input  
CP  
CEP  
Count Enable Parallel Input (Active LOW)  
D0/CET  
Serial Data Input/Count Enable Trickle  
Input (Active LOW)  
24 23 22 21 20 19  
18  
1
2
3
4
5
6
S2  
CEP  
D0/CET  
TC  
P1  
P2  
P3  
D3  
Q3  
Q3  
17  
16  
15  
14  
13  
S0 — S2  
MR  
Select Inputs  
Top View  
Flatpack  
F24-1  
Master Reset Input  
VEE Substrate  
VEES  
Q0  
VCCA  
VCCO for ECL Outputs  
Preset Inputs  
Q0  
7
8 9 10 11 12  
P0 – P3  
D3  
Serial Data Input  
Terminal Count Output  
Data Outputs  
TC  
Q0 — Q3  
Q0 — Q3  
Complementary Data Outputs  
Rev.: G  
Amendment:/0  
Issue Date: July, 1999  
1
1234567...9

中文翻译

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