SY100S331
SY100S331
Micrel, Inc.
TRIPLE D
FLIP-FLOP
FEATURES
DESCRIPTION
The SY100S331 offers three D-type, edge-triggered
master/slave flip-flops with true and complement outputs,
designed for use in high-performance ECL systems. Each
flip-flop is controlled by a common clock (CPc), as well as
its own clock pulse (CPn). The resultant clock signal
controlling the flip-flop is the logical OR operation of these
two clock signals. Data enters the master when both CPc
and CPn are LOW and enters the slave on the rising edge
of either CPc or CPn (or both).
■ Max. toggle frequency of 800MHz
■ Differential outputs
■ IEE min. of –80mA
■ Industry standard 100K ECL levels
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved
noise immunity
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SDn) and Direct Clear (CDn) signals. The MR,
MS, SDn and DCn signals override the clock signals. The
inputs on this device have 75KΩ pull-down resistors.
■ Internal 75KΩ input pull-down resistors
■ 150% faster than Fairchild
■ 40% lower power than Fairchild
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
PIN NAMES
Pin
CP0 – CP2
CPc
Function
Individual Clock Inputs
Common Clock Input
Data Inputs
CD
CP
2
CD
SD
CD
SD
CD
SD
C
Q
Q
2
2
CP
D
CP
2
2
2
1
D
D0 – D2
CD0 – CD2
SDn
SD
CD
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Q
Q
1
1
CP
D
MR
CP
1
1
1
0
MS
D
Q0 – Q2
Q0 – Q2
VEES
Data Outputs
SD
CD
Complementary Data Outputs
VEE Substrate
Q
Q
0
0
CP
D
CP
0
0
0
VCCA
VCCO for ECL Outputs
D
SD
MS MR
Rev.: H
Amendment:/0
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
1
Issue Date: March 2006