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SY100S325JY

更新时间： 2024-11-11 05:04:27

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
6页	503K
描述
LOW-POWER HEX ECL-to-TTL TRANSLATOR

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数据手册

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SY100S325JY 数据手册

LOW-POWERHEX

ECL-to-TTL

TRANSLATOR

Micrel, Inc.

SY100S325

DESCRIPTION

FEATURES

■ Max. propagation delay of 3.7ns

■ IEE min. of –37mA

The SY100S325 are hex translators for converting

100K ECL logic levels to TTL logic levels. Inputs can be

used as inverting, non-inverting or differential receivers.

An internal reference voltage generator provides VBB for

single-ended operation or for use in Schmitt trigger

applications. All inputs have 75KΩ pull-down resistors.

The outputs will go LOW when the inputs are either open

or have the same potential.

■ TTL outputs

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ 25% faster than National's 325

■ Differential inputs with built-in offset

When used in single-ended operation, the apparent

input threshold of the true inputs is 20mV to 40mV higher

(positive) than the threshold of the complementary inputs.

The VTTL and VEE power may be applied in either order.

■ Voltage and temperature compensation for improved

noise immunity

■ VBB output for single-ended use

■ Internal 75KΩ input pull-down resistors

■ Function and pinout compatible with Fairchild F100K

■ Available in 24-pin CERPACK and 28-pin PLCC

packages

PIN NAMES

BLOCK DIAGRAM

D0–D5

Function

Data Inputs

D0–D5

Q0–Q5

VEES

Inverting Data Inputs

Data Outputs

VEE Substrate

VTTL

TTL VCC Power Supply

VCCO for ECL Outputs

VCCA

Rev.: H

Amendment:/0

M9999-061306

hbwhelp@micrel.com or (408) 955-1690

Issue Date: June 2006

12 3 4 5 6

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