SY100S331JC

更新时间： 2024-11-10 22:59:23

品牌	Logo	应用领域
麦瑞 - MICREL		触发器逻辑集成电路
页数	文件大小	规格书
7页	113K
描述
TRIPLE D FLIP-FLOP

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中文翻译

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数据手册

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SY100S331JC 数据手册

TRIPLE D

FLIP-FLOP

SY100S331

FEATURES

DESCRIPTION

The SY100S331 offers three D-type, edge-triggered

master/slave flip-flops with true and complement outputs,

designed for use in high-performance ECL systems. Each

flip-flop is controlled by a common clock (CPc), as well as

its own clock pulse (CPn). The resultant clock signal

controlling the flip-flop is the logical OR operation of these

two clock signals. Data enters the master when both CPc

and CPn are LOW and enters the slave on the rising edge

of either CPc or CPn (or both).

■ Max. toggle frequency of 800MHz

■ Differential outputs

■ IEE min. of –80mA

■ Industry standard 100K ECL levels

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for improved

noise immunity

Additional control signals include Master Set (MS) and

Master Reset (MR) inputs. Each flip-flop also has its own

Direct Set (SDn) and Direct Clear (CDn) signals. The MR,

MS, SDn and DCn signals override the clock signals. The

inputs on this device have 75KΩ pull-down resistors.

■ Internal 75KΩ input pull-down resistors

■ 150% faster than Fairchild

■ 40% lower power than Fairchild

■ Function and pinout compatible with Fairchild F100K

■ Available in 24-pin CERPACK and 28-pin PLCC

packages

PIN CONFIGURATIONS

BLOCK DIAGRAM

11 10 9

8 7 6 5

CPC

VEE

CCA

Top View

PLCC

J28-1

VEES

19 20 21 22 23 24 25

24 23 22 21 20 19

Top View

Flatpack

F24-1

CP2

9 10 11 12

MS MR

Rev.: G

Amendment:/0

Issue Date: July, 1999

12 3 4 5 6 7

中文翻译

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