SY100EL34LZCTR

更新时间： 2024-09-20 22:16:19

品牌	Logo	应用领域
麦瑞 - MICREL		时钟发生器逻辑集成电路光电二极管驱动
页数	文件大小	规格书
4页	60K
描述
5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP

阅读下载

中文翻译

获取价格

技术参数
数据手册
替代型号

如果您发现信息不准确，欢迎纠错

SY100EL34LZCTR 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	0.150 INCH, SOIC-16	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.34
系列：	100EL	输入调节：	DIFFERENTIAL
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	16
实输出次数：	3	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	OPEN-EMITTER
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	-3.3 V
最大电源电流（ICC）：	54 mA	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.05 ns	子类别：	Clock Drivers
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

SY100EL34LZCTR 数据手册

ClockWorks™

SY10EL34/L

SY100EL34/L

5V/3.3V ÷2, ÷4, ÷8 CLOCK

GENERATION CHIP

FEATURES

DESCRIPTION

■ 3.3V and 5V power supply options

■ 50ps output-to-output skew

The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock

generation chips designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the VBB output, a sinusoidal source can be AC-

coupled into the device. If a single-ended input is to be

used, the VBB output should be connected to the CLK

input and bypassed to ground via a 0.01µF capacitor.

The VBB output is designed to act as the switching

reference for the input of the EL34/L under single-ended

input conditions. As a result, this pin can only source/

sink up to 0.5mA of current.

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the divider stages. The

internal enable flip-flop is clocked on the falling edge of

the input clock, therefore, all associated specification

limits are referenced to the negative edge of the clock

input.

■ Synchronous enable/disable

■ Master Reset for synchronization

■ Internal 75KΩ input pull-down resistors

■ Available in 16-pin SOIC package

PIN CONFIGURATION/BLOCK DIAGRAM

VCC

÷2

VCC

14 NC

CLK

÷4

CLK

V^BB

VCC

10 MR

÷8

V^EE

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL34/Ls in a system.

SOIC

TOP VIEW

PIN NAMES

CLK

VBB

Function

Differential Clock Inputs

Synchronous Enable

Master Reset

Reference Output

Differential ÷2 Outputs

Differential ÷4 Outputs

Differential ÷8 Outputs

Rev.: F

Amendment:/0

Issue Date: August, 1998

12 3 4

中文翻译

下载PDF

SY100EL34LZCTR 替代型号

型号	品牌	替代类型	描述	数据表
MC100EL34DG	ONSEMI	类似代替	5V ECL ±2, ±4, ±8 Clock Generation Chip
MC10EL34DR2G	ONSEMI	类似代替	5V ECL ±2, ±4, ±8 Clock Generation Chip

与SY100EL34LZCTR相关器件

型号	品牌	获取价格	描述	数据表
SY100EL34LZG	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34LZG	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL34LZGTR	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34LZG-TR	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL34LZI	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34LZITR	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34ZC	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34ZCTR	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34ZG	MICREL	获取价格	5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip
SY100EL34ZG	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

与SY100EL34LZCTR相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

34
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

31
SL74HC10N：高性能三输入与非门解析
2024-09-03

104
AIC1781A 电池充电控制器深度解析
2024-09-03

100

产品中心

服务支持

精选活动

关于我们

帮助中心

SY100EL34LZCTR

SY100EL34LZCTR 技术参数

SY100EL34LZCTR 数据手册

SY100EL34LZCTR 替代型号

与SY100EL34LZCTR相关器件

与SY100EL34LZCTR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SY100EL34LZCTR

SY100EL34LZCTR 技术参数

SY100EL34LZCTR 数据手册

SY100EL34LZCTR 替代型号

与SY100EL34LZCTR相关器件

与SY100EL34LZCTR相关文章

您还可以找

您在本页遇到什么问题？