Datasheet > SY100EL34ZG

SY100EL34ZG

更新时间： 2024-01-12 20:54:49

品牌	Logo	应用领域
美国微芯 - MICROCHIP		驱动光电二极管输出元件逻辑集成电路
页数	文件大小	规格书
7页	209K
描述
100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

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SY100EL34ZG 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	SOP,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	Factory Lead Time：	7 weeks
风险等级：	1.5	Is Samacsys：	N
系列：	100EL	输入调节：	DIFFERENTIAL
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e4
长度：	9.93 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	16	实输出次数：	3
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	1.2 ns
Same Edge Skew-Max（tskwd）：	0.05 ns	座面最大高度：	1.73 mm
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.94 mm	Base Number Matches：	1

SY100EL34ZG 数据手册

NOT RECOMMENDED FOR NEW DESIGNS

SY10EL34/L

SY100EL34/L

5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip

Precision Edge^®

General Description

The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock

generation chips designed explicitly for low-skew clock

generation applications. The internal dividers are

synchronous to each other; therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the V_BBoutput, a sinusoidal source can be AC-

coupled into the device. If a single-ended input is to be

Precision Edge^®

Features

• 3.3V and 5V power supply options

• 50ps output-to-output skew

• Synchronous enable/disable

• Master Reset for synchronization

• Internal 75KΩ input pull-down resistors

• Available in 16-pin SOIC package

used, the V_BBoutput should be connected to the CLK

input and bypassed to ground via a 0.01µF capacitor. The

V_BBoutput is designed to act as the switching reference for

the input of the EL34/L under single-ended input

conditions. As a result, this pin can only source/ sink up to

0.5mA of current.

Pin Description

Pin Name Pin Function

CLK

Differential clock inputs.

Synchronous enable.

The common enable (EN ) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids any

chance of generating a runt clock pulse on the internal

clock when the device is enabled/disabled as can happen

with an asynchronous control. An internal runt pulse could

lead to losing synchronization between the internal divider

stages. The internal enable flip-flop is clocked on the

falling edge of the divider stages. The internal enable flip-

flop is clocked on the falling edge of the input clock;

therefore, all associated specification limits are referenced

to the negative edge of the clock input.

V_BB

Q₀

Master reset.

Reference output.

Differential ÷2 outputs.

Differential ÷4 outputs.

Differential ÷8 outputs.

Q₁

Q₂

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL34/Ls in a system.

Data sheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

M9999-120611-I

December 2011

hbwhelp@micrel.com or (408) 955-1690

12 3 4 5 6 7

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SY100EL34ZG 替代型号

型号	品牌	替代类型	描述	数据表
SY100EL34ZG-TR	MICROCHIP	完全替代	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL34LZG	MICROCHIP	类似代替	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

与SY100EL34ZG相关器件

型号	品牌	获取价格	描述	数据表
SY100EL34ZGTR	MICREL	获取价格	5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip
SY100EL34ZG-TR	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL35	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZC	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZCTR	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZG	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZGTR	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZI	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZITR	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZITR	MICROCHIP	获取价格	100EL SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, 0.150 IN

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