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SY100EL35LZI-TR PDF预览

SY100EL35LZI-TR

更新时间: 2024-01-06 13:01:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
4页 46K
描述
100EL SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8

SY100EL35LZI-TR 技术参数

生命周期:Active包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.61系列:100EL
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.93 mm逻辑集成电路类型:J-K FLIP-FLOP
位数:2功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):0.7 ns认证状态:Not Qualified
座面最大高度:1.73 mm表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:3.94 mm
最小 fmax:1800 MHzBase Number Matches:1

SY100EL35LZI-TR 数据手册

 浏览型号SY100EL35LZI-TR的Datasheet PDF文件第2页浏览型号SY100EL35LZI-TR的Datasheet PDF文件第3页浏览型号SY100EL35LZI-TR的Datasheet PDF文件第4页 
5  
5  
SY10EL35  
JK FLIP-FLOP  
SY100EL35  
FEATURES  
DESCRIPTION  
525ps propagation delay  
The SY10/100EL35 are high-speed JK Flip-Flops. The  
J/K data enters the master portion of the flip-flop when  
the clock is LOW and is transferred to the slave and,  
thus, the outputs, upon a positive transition of the clock.  
The reset pin is asynchronous and is activated with a  
logic HIGH.  
2.2GHz toggle frequency  
High bandwidth output transistions  
Internal 75Kinput pull-down resistors  
Available in 8-pin SOIC package  
(1)  
TRUTH TABLE  
J
L
K
L
R
L
L
L
L
H
CLK  
Z
Qn+1  
Qn  
L
L
H
L
Z
H
H
X
Z
H
H
X
Z
Qn  
L
X
NOTE:  
1. Z = LOW-to-HIGH transition.  
Rev.: G  
Amendment:/0  
M9999-121205  
hbwhelp@micrel.com or (408) 955-1690  
1
1
Issue Date: December2005  

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