Datasheet > SY100EL52

SY100EL52

更新时间： 2024-11-30 14:55:03

品牌	Logo	应用领域
美国微芯 - MICROCHIP		局域网（LAN）标准
页数	文件大小	规格书
14页	241K
描述
The SY10/100EL52 are differential data, differential clock D flip-flops. These devices are functio

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SY100EL52 数据手册

SY100EL52

5V ECL Differential Data and Clock D Flip-Flop

Features

General Description

• 365 ps Propagation Delay (typical)

• 2.8 GHz Toggle Frequency (typical)

• Internal 75 kΩ Input Pull-Down Resistors

• Available in 8-Lead SOIC Package

The SY100EL52 is a differential data, differential clock

D flip-flop. Data enters the master portion of the flip-flop

when the clock is low and is transferred to the slave,

then the outputs, upon a positive transition of the clock.

The differential clock inputs also allow the EL52 to be

used as a negative edge triggered device.

The EL52 employs input clamping circuitry so that,

under open input conditions (pulled down to V_EE), the

outputs of the device will remain stable.

Package Type

SY100EL52

8-Lead SOIC (Z)

V_CC

Flip-Flop

CLK

V_EE

 2018 Microchip Technology Inc.

DS20006066A-page 1

12 3 4 5 6 7...14

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