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SY100EL57LZCTR PDF预览

SY100EL57LZCTR

更新时间: 2024-11-01 22:07:39
品牌 Logo 应用领域
麦瑞 - MICREL 解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 65K
描述
3.3V 4:1 DIFFERENTIAL MULTIPLEXER

SY100EL57LZCTR 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.36
Is Samacsys:N系列:100EL
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm逻辑集成电路类型:MULTIPLEXER
湿度敏感等级:1功能数量:1
输入次数:4输出次数:1
端子数量:16最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
传播延迟(tpd):0.56 ns认证状态:Not Qualified
座面最大高度:1.75 mm表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

SY100EL57LZCTR 数据手册

 浏览型号SY100EL57LZCTR的Datasheet PDF文件第2页浏览型号SY100EL57LZCTR的Datasheet PDF文件第3页浏览型号SY100EL57LZCTR的Datasheet PDF文件第4页 
3.3V 4:1 DIFFERENTIAL  
MULTIPLEXER  
SY100EL57L  
FEATURES  
DESCRIPTION  
3.3V power supply  
The SY100EL57L is a full differential 4:1 multiplexer.  
By leaving the SEL1 line open (pulled LOW via the input  
pulldown resistors) the device can also be used as a  
differential 2:1 multiplexer with SEL0 input selecting between  
D0 and D1. The fully differential architecture of the EL57L  
makes it ideal for use in low skew applications such as  
clock distribution.  
Useful as either 4:1 or 2:1 multiplexer  
VBB output for single-ended operation  
75Kinternal input pulldown resistors  
Available in 150 mil 16-pin SOIC package  
The SEL1 is the most significant select line. The binary  
number applied to the select inputs will select the same  
numbered data input (i.e., 00 selects D0).  
Multiple VBB outputs are provided for single-ended or  
AC coupled interfaces. In these scenarios, the VBB output  
should be connected to the data bar inputs and bypassed  
via a 0.01µF capacitor to ground. Note that the VBB output  
can source/sink up to 0.5mA of current without upsetting  
the voltage level.  
PIN CONFIGURATION/BLOCK DIAGRAM  
VCC  
SEL0 SEL1  
Q
Q
V
BB1  
VBB2  
V
EE  
9
16  
15  
14  
13  
12  
11  
10  
4:1  
1
2
3
4
5
6
7
8
D0  
D0  
D1  
D1  
D2  
D2  
D3  
D3  
SOIC  
TOP VIEW  
TRUTH TABLE  
PIN NAMES  
Pin  
Function  
Differential Data Inputs  
Mux Select Inputs  
Reference Outputs  
Data Outputs  
SEL1  
SEL0  
DATA OUT  
D0-3  
SEL0, 1  
VBB1, 2  
Q
L
L
L
H
L
D0  
D1  
D2  
D3  
H
H
H
Rev.: A  
Amendment: /0  
Issue Date: March, 1999  
1

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