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SY100EL38LZCTR

更新时间： 2024-11-29 08:57:03
品牌 Logo 应用领域
麦瑞 - MICREL 时钟
页数 文件大小 规格书
6页 70K
描述
5V/3.3V ÷2, ÷4/6 CLOCK GENERATION CHIP

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中文翻译

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SY100EL38LZCTR 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：SOP, SOP20,.4Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.23
系列：100EL输入调节：DIFFERENTIAL
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：12.83 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：20
实输出次数：4最高工作温度：70 °C
最低工作温度：输出特性：OPEN-EMITTER
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：240
电源：-3.3 VProp。Delay @ Nom-Sup：1.3 ns
传播延迟（tpd）：1.22 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.075 ns座面最大高度：2.65 mm
子类别：Clock Drivers表面贴装：YES
技术：ECL温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.52 mm
最小 fmax：1000 MHzBase Number Matches：1

SY100EL38LZCTR 数据手册

 浏览型号SY100EL38LZCTR的Datasheet PDF文件第2页浏览型号SY100EL38LZCTR的Datasheet PDF文件第3页浏览型号SY100EL38LZCTR的Datasheet PDF文件第4页浏览型号SY100EL38LZCTR的Datasheet PDF文件第5页浏览型号SY100EL38LZCTR的Datasheet PDF文件第6页 
SY10EL38/L  
SY100EL38/L  
®
Precision Edge  
5V/3.3V ÷2, ÷4/6 CLOCK  
GENERATION CHIP  
FEATURES  
ꢀ 3.3V and 5V power supply options  
ꢀ 50ps output-to-output skew  
®
Precision Edge  
ꢀ Synchronous enable/disable  
DESCRIPTION  
ꢀ Master Reset for synchronization  
ꢀ Internal 75KΩ input pull-down resistors  
ꢀ Available in 20-pin SOIC package  
The SY10/100EL38/L are low skew ÷2, ÷4/6 clock  
generation chips designed explicitly for low skew clock  
generation applications. The internal dividers are  
synchronous to each other, therefore, the common output  
edges are all precisely aligned. The devices can be driven  
by either a differential or single-ended ECL or, if positive  
power supplies are used, PECL input signal. In addition,  
by using the VBB output, a sinusoidal source can be AC-  
coupled into the device. If a single-ended input is to be  
used, the VBB output should be connected to the CLK  
input and bypassed to ground via a 0.01µF capacitor.  
The VBB output is designed to act as the switching  
reference for the input of the EL38/L under single-ended  
input conditions. As a result, this pin can only source/  
sink up to 0.5mA of current.  
The common enable (EN) is synchronous so that the  
internal dividers will only be enabled/disabled when the  
internal clock is already in the LOW state. This avoids  
any chance of generating a runt clock pulse on the  
internal clock when the device is enabled/disabled as  
can happen with an asynchronous control. An internal  
runt pulse could lead to losing synchronization between  
the internal divider stages. The internal enable flip-flop is  
clocked on the falling edge of the input clock, therefore,  
all associated specification limits are referenced to the  
negative edge of the clock input.  
The Phase_Out output will go HIGH for one clock cycle  
whenever the ÷2 and the ÷4/6 outputs are both  
transitioning from a LOW to a HIGH. This output allows  
for clock synchronization within the system.  
Upon start-up, the internal flip-flops will attain a  
random state; the master reset (MR) input allows for the  
synchronization of the internal dividers, as well as for  
multiple EL38/Ls in a system.  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: G  
Amendment:/0  
M9999-031006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  
123456

中文翻译

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SY100EL38LZCTR 替代型号

型号 品牌 替代类型 描述 数据表
SY100EL38LZITR MICREL

完全替代

 5V/3.3V ÷2, ÷4/6 CLOCK GENERATION CHIP
MC100LVEL38DWR2G ONSEMI

类似代替

 3.3V ECL ±2, ±4/6 Clock Generation Chip
MC100LVEL38DWG ONSEMI

类似代替

 3.3V ECL ±2, ±4/6 Clock Generation Chip

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