SY100EL38LZI

更新时间： 2024-11-29 08:57:03

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
6页	70K
描述
5V/3.3V ÷2, ÷4/6 CLOCK GENERATION CHIP

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SY100EL38LZI 数据手册

Precision Edge^®

SY10EL38/L

SY100EL38/L

SY10EL38/L

SY100EL38/L

Precision Edge

Micrel, Inc.

5V/3.3V ÷2, ÷4/6 CLOCK

GENERATION CHIP

FEATURES

ꢀ 3.3V and 5V power supply options

ꢀ 50ps output-to-output skew

Precision Edge

ꢀ Synchronous enable/disable

DESCRIPTION

ꢀ Master Reset for synchronization

ꢀ Internal 75KΩ input pull-down resistors

ꢀ Available in 20-pin SOIC package

The SY10/100EL38/L are low skew ÷2, ÷4/6 clock

generation chips designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the VBB output, a sinusoidal source can be AC-

coupled into the device. If a single-ended input is to be

used, the VBB output should be connected to the CLK

input and bypassed to ground via a 0.01µF capacitor.

The VBB output is designed to act as the switching

reference for the input of the EL38/L under single-ended

input conditions. As a result, this pin can only source/

sink up to 0.5mA of current.

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the

negative edge of the clock input.

The Phase_Out output will go HIGH for one clock cycle

whenever the ÷2 and the ÷4/6 outputs are both

transitioning from a LOW to a HIGH. This output allows

for clock synchronization within the system.

Upon start-up, the internal flip-flops will attain a

random state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL38/Ls in a system.

Precision Edge is a registered trademark of Micrel, Inc.

Rev.: G

Amendment:/0

M9999-031006

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5 6

中文翻译

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SY100EL38LZI 替代型号

型号	品牌	替代类型	描述	数据表
SY100EL38LZITR	MICREL	完全替代	5V/3.3V ÷2, ÷4/6 CLOCK GENERATION CHIP
MC100LVEL38DWR2G	ONSEMI	类似代替	3.3V ECL ±2, ±4/6 Clock Generation Chip
MC100LVEL38DWG	ONSEMI	类似代替	3.3V ECL ±2, ±4/6 Clock Generation Chip

与SY100EL38LZI相关器件

型号	品牌	获取价格	描述	数据表
SY100EL38LZITR	MICREL	获取价格	5V/3.3V ÷2, ÷4/6 CLOCK GENERATION CHIP
SY100EL51	MICREL	获取价格	DIFFERENTIAL CLOCK D FLIP-FLOP
SY100EL51ZC	MICREL	获取价格	DIFFERENTIAL CLOCK D FLIP-FLOP
SY100EL51ZC	MICROCHIP	获取价格	D Flip-Flop, 100EL Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, E
SY100EL51ZCTR	MICREL	获取价格	DIFFERENTIAL CLOCK D FLIP-FLOP
SY100EL51ZG	MICREL	获取价格	DIFFERENTIAL CLOCK D FLIP-FLOP
SY100EL51ZG	MICROCHIP	获取价格	100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
SY100EL51ZGTR	MICREL	获取价格	DIFFERENTIAL CLOCK D FLIP-FLOP
SY100EL51ZG-TR	MICROCHIP	获取价格	100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
SY100EL51ZI	MICREL	获取价格	DIFFERENTIAL CLOCK D FLIP-FLOP

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