SY100EL34ZC

更新时间： 2024-02-16 04:43:16

品牌	Logo	应用领域
麦瑞 - MICREL		时钟驱动器时钟发生器逻辑集成电路光电二极管
页数	文件大小	规格书
4页	60K
描述
5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP

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中文翻译

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技术参数
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替代型号

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SY100EL34ZC 技术参数

生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	7 weeks
风险等级：	5.65	Is Samacsys：	N
系列：	100EL	输入调节：	DIFFERENTIAL
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e4
长度：	9.93 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	16	实输出次数：	6
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
传播延迟（tpd）：	1.2 ns	Same Edge Skew-Max（tskwd）：	0.05 ns
座面最大高度：	1.73 mm	表面贴装：	YES
技术：	ECL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	3.94 mm
Base Number Matches：	1

SY100EL34ZC 数据手册

ClockWorks™

SY10EL34/L

SY100EL34/L

5V/3.3V ÷2, ÷4, ÷8 CLOCK

GENERATION CHIP

FEATURES

DESCRIPTION

■ 3.3V and 5V power supply options

■ 50ps output-to-output skew

The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock

generation chips designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the VBB output, a sinusoidal source can be AC-

coupled into the device. If a single-ended input is to be

used, the VBB output should be connected to the CLK

input and bypassed to ground via a 0.01µF capacitor.

The VBB output is designed to act as the switching

reference for the input of the EL34/L under single-ended

input conditions. As a result, this pin can only source/

sink up to 0.5mA of current.

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the divider stages. The

internal enable flip-flop is clocked on the falling edge of

the input clock, therefore, all associated specification

limits are referenced to the negative edge of the clock

input.

■ Synchronous enable/disable

■ Master Reset for synchronization

■ Internal 75KΩ input pull-down resistors

■ Available in 16-pin SOIC package

PIN CONFIGURATION/BLOCK DIAGRAM

VCC

÷2

VCC

14 NC

CLK

÷4

CLK

V^BB

VCC

10 MR

÷8

V^EE

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL34/Ls in a system.

SOIC

TOP VIEW

PIN NAMES

CLK

VBB

Function

Differential Clock Inputs

Synchronous Enable

Master Reset

Reference Output

Differential ÷2 Outputs

Differential ÷4 Outputs

Differential ÷8 Outputs

Rev.: F

Amendment:/0

Issue Date: August, 1998

12 3 4

中文翻译

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SY100EL34ZC 替代型号

型号	品牌	替代类型	描述	数据表
SY10EL34ZCTR	MICREL	完全替代	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
MC100EL34DR2G	ONSEMI	类似代替	5V ECL ±2, ±4, ±8 Clock Generation Chip
MC10EL34DR2G	ONSEMI	类似代替	5V ECL ±2, ±4, ±8 Clock Generation Chip

与SY100EL34ZC相关器件

型号	品牌	获取价格	描述	数据表
SY100EL34ZCTR	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34ZG	MICREL	获取价格	5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip
SY100EL34ZG	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL34ZGTR	MICREL	获取价格	5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip
SY100EL34ZG-TR	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL35	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZC	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZCTR	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZG	MICREL	获取价格	JK FLIP-FLOP
SY100EL35LZGTR	MICREL	获取价格	JK FLIP-FLOP

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