MC100EL34DR2G

更新时间： 2024-01-24 23:55:07

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
8页	133K
描述
5V ECL ±2, ±4, ±8 Clock Generation Chip

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替代型号

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MC100EL34DR2G 数据手册

MC10EL34, MC100EL34

5VꢀECL ÷2, ÷4, ÷8 Clock

Generation Chip

Description

The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

http://onsemi.com

output edges are all precisely aligned. The V pin, an internally

generated voltage supply, is available to this device only. For

single-ended input conditions, the unused differential input is

connected to V as a switching reference voltage. V may also

rebias AC coupled inputs. When used, decouple V and V via a

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.

When not used, V should be left open.

SO−16

D SUFFIX

CASE 751B

The common enable (EN) is synchronous so that the internal

dividers will only be enabled/disabled when the internal clock is

already in the LOW state. This avoids any chance of generating a runt

clock pulse on the internal clock when the device is enabled/disabled

as can happen with an asynchronous control. An internal runt pulse

could lead to losing synchronization between the internal divider

stages. The internal enable flip−flop is clocked on the falling edge of

the input clock, therefore, all associated specification limits are

referenced to the negative edge of the clock input.

MARKING DIAGRAMS*

10EL34G

AWLYWW

100EL34G

AWLYWW

Upon startup, the internal flip-flops will attain a random state; the

master reset (MR) input allows for the synchronization of the internal

dividers, as well as multiple EL34s in a system.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The 100 Series contains temperature compensation.

Features

• 50 ps Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• PECL Mode Operating Range:

*For additional marking information, refer to

Application Note AND8002/D.

= 4.2 V to 5.7 V with V = 0 V

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

• NECL Mode Operating Range:

= 0 V with V = −4.2 V to −5.7 V

• Internal Input 75 kW Pulldown Resistors on CLK(s), EN, and MR

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 10

MC10EL34/D

12 3 4 5 6 7 8

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MC100EL34DR2G 替代型号

型号	品牌	替代类型	描述	数据表
MC100EL34DG	ONSEMI	完全替代	5V ECL ±2, ±4, ±8 Clock Generation Chip
MC10EL34DG	ONSEMI	完全替代	5V ECL ±2, ±4, ±8 Clock Generation Chip

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