Datasheet > MC100EL38_06

MC100EL38_06

更新时间： 2024-11-27 05:22:27

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
7页	123K
描述
5V ECL ±2, ±4/6 Clock Generation Chip

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MC100EL38_06 数据手册

MC100EL38

5VꢀECL ÷2, ÷4/6 Clock

Generation Chip

The MC100EL38 is a low skew ÷2, ÷4/6 clock generation chip

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by

either a differential or single-ended ECL or, if positive power supplies

are used, PECL input signal.

http://onsemi.com

The V pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

SO−20 WB

DW SUFFIX

CASE 751D

to 0.5 mA. When not used, V should be left open.

The common enable (EN) is synchronous so that the internal

dividers will only be enabled/disabled when the internal clock is

already in the LOW state. This avoids any chance of generating a runt

clock pulse on the internal clock when the device is enabled/disabled

as can happen with an asynchronous control. An internal runt pulse

could lead to losing synchronization between the internal divider

stages. The internal enable flip−flop is clocked on the falling edge of

the input clock, therefore, all associated specification limits are

referenced to the negative edge of the clock input.

MARKING DIAGRAM*

100EL38

AWLYYWWG

The Phase_Out output will go HIGH for one clock cycle whenever

the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a

HIGH. This output allows for clock synchronization within the system.

Upon startup, the internal flip-flops will attain a random state;

therefore, for systems which utilize multiple EL38s, the master reset

(MR) input must be asserted to ensure synchronization. For systems

which only use one EL38, the MR pin need not be exercised as the

internal divider design ensures synchronization between the ÷2 and

the ÷4/6 outputs of a single device.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

• 50 ps Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• ESD Protection: > 2 kV Human Body Model,

> 100 V Machine Model

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

• The 100 Series Contains Temperature Compensation

• PECL Mode Operating Range: V = 4.2 V to 5.7 V

• Moisture Sensitivity Level 1

with V = 0 V

For Additional Information, see Application Note

AND8003/D

• NECL Mode Operating Range: V = 0 V with

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 388 devices

• Pb−Free Packages are Available*

= −4.2 V to −5.7 V

• Internal 75 kW Input Pulldown Resistors on CLK, EN,

MR, and DIVSEL

• Q Output will Default LOW with Inputs Open or at

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

October, 2006 − Rev. 7

MC100EL38/D

12 3 4 5 6 7

中文翻译

下载PDF

与MC100EL38_06相关器件

型号	品牌	获取价格	描述	数据表
MC100EL38DW	ONSEMI	获取价格	5V ECL ±2, ±4/6 Clock Generation Chip
MC100EL38DW	MOTOROLA	获取价格	±2, ±4/6 Clock Generation Chip
MC100EL38DWG	ONSEMI	获取价格	5V ECL ±2, ±4/6 Clock Generation Chip
MC100EL38DWR2	ONSEMI	获取价格	5V ECL ±2, ±4/6 Clock Generation Chip
MC100EL38DWR2	MOTOROLA	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, PLAST
MC100EL38DWR2G	ONSEMI	获取价格	5V ECL ±2, ±4/6 Clock Generation Chip
MC100EL39	MOTOROLA	获取价格	±2/4,±4/6 Clock Generation Chip
MC100EL39	ONSEMI	获取价格	±2/4, ±4/6 Clock Generation Chip
MC100EL39DW	MOTOROLA	获取价格	±2/4,±4/6 Clock Generation Chip
MC100EL39DW	ONSEMI	获取价格	5V ECL ±2/4, ±4/6 Clock Generation Chip

与MC100EL38_06相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

46
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

34
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

63
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

60

产品中心

服务支持

精选活动

关于我们

帮助中心

MC100EL38_06

MC100EL38_06 数据手册

与MC100EL38_06相关器件

与MC100EL38_06相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MC100EL38_06

MC100EL38_06 数据手册

与MC100EL38_06相关器件

与MC100EL38_06相关文章

您还可以找

您在本页遇到什么问题？