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MC100EL51 PDF预览

MC100EL51

更新时间: 2024-01-29 15:24:28
品牌 Logo 应用领域
安森美 - ONSEMI 触发器时钟
页数 文件大小 规格书
3页 84K
描述
Differential Clock D Flip-Flop

MC100EL51 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:LEAD FREE, PLASTIC, TSSOP-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:7.87
Is Samacsys:N其他特性:NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V
系列:100ELJESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:1800000000 Hz
湿度敏感等级:3位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:RAIL峰值回流温度(摄氏度):260
电源:-4.5 V最大电源电流(ICC):36 mA
Prop。Delay @ Nom-Sup:0.62 ns传播延迟(tpd):0.565 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:FF/Latches最大供电电压 (Vsup):5.7 V
最小供电电压 (Vsup):4.2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:3 mm
最小 fmax:2200 MHzBase Number Matches:1

MC100EL51 数据手册

 浏览型号MC100EL51的Datasheet PDF文件第2页浏览型号MC100EL51的Datasheet PDF文件第3页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10EL/100EL51 is a differential clock D flip-flop with reset. The  
device is functionally similar to the E151 device with higher performance  
capabilities. With propagation delays and output transition times  
significantly faster than the E151 the EL51 is ideally suited for those  
applications which require the ultimate in AC performance.  
The reset input is an asynchronous, level triggered signal. Data enters  
the master portion of the flip-flop when the clock is LOW and is  
transferred to the slave, and thus the outputs, upon a positive transition of  
the clock. The differential clock inputs of the EL51 allow the device to be  
used as a negative edge triggered flip-flop.  
The differential input employs clamp circuitry to maintain stability under  
8
open input (pulled down to V ) conditions.  
EE  
1
475ps Propagation Delay  
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751-05  
2.8GHz Toggle Frequency  
75kInternal Input Pulldown Resistors  
>1000V ESD Protection  
LOGIC DIAGRAM AND PINOUT ASSIGNMENT  
R 1  
8
7
V
CC  
R
D
2
3
D
Q
Q
TRUTH TABLE  
D
L
R
L
CLK  
Z
Q
L
Flip-Flop  
CLK  
6
5
H
X
L
Z
H
L
CLK  
4
V
EE  
H
X
Z = LOW to HIGH Transition  
12/93  
Motorola, Inc. 1996  
REV 2  

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