MC100EL38

更新时间： 2024-11-01 23:01:31

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
5页	131K
描述
±2, ±4/6 Clock Generation Chip

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MC100EL38 数据手册

SEMICONDUCTOR TECHNICAL DATA

÷ ÷

The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip

designed explicitly for low skew clock generation applications. The

MC100EL38 is pin and functionally equivalent to the MC100LVEL38 but

is specified for operation at the standard 100K ECL voltage supply. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by either

a differential or single-ended LVECL or, if positive power supplies are

used, LVPECL input signal. In addition, by using the V

sinusoidal source can be AC coupled into the device (see Interfacing

section of the ECLinPS Data Book DL140/D). If a single-ended input is

output, a

to be used, the V

output should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. The V

output is designed to

act as the switching reference for the input of the LVEL38 under

single-ended input conditions, as a result, this pin can only source/sink up

to 0.5mA of current.

The common enable (EN) is synchronous so that the internal dividers

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen

with an asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip-flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

The Phase_Out output will go HIGH for one clock cycle whenever the

÷2 and the ÷4/6 outputs are both transitioning from a LOW to a HIGH.

This output allows for clock synchronization within the system.

PIN DESCRIPTION

FUNCTION

Upon startup, the internal flip-flops will attain a random state; therefore,

for systems which utilize multiple LVEL38s, the master reset (MR) input

must be asserted to ensure synchronization. For systems which only use

one LVEL38, the MR pin need not be exercised as the internal divider

design ensures synchronization between the ÷2 and the ÷4/6 outputs of a

single device.

CLK

Diff Clock Inputs

Sync Enable

Master Reset

Reference Output

Diff ÷2 Outputs

Diff ÷4/6 Outputs

Frequency Select Input

Q , Q

DIVSEL

• 50ps Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• 75kΩ Internal Input Pulldown Resistors

• >1500V ESD Protection

Phase_Out

Phase Sync Signal

FUNCTION TABLE

CLK

FUNCTION

• Low Voltage V

Range of –3.0 to –3.8V

Divide

Hold Q

0–3

Reset Q

Pinout: 20-Lead SOIC (Top View)

0–3

Z = Low-to-High Transition

ZZ = High-to-Low Transition

DIVSEL

Q , Q OUTPUTS

2 3

Divide by 4

Divide by 6

EN DIV_SEL CLK CLK

10/94

Motorola, Inc. 1996

REV 1

4–1

12 3 4 5

中文翻译

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与MC100EL38相关器件

型号	品牌	获取价格	描述	数据表
MC100EL38_06	ONSEMI	获取价格	5V ECL ±2, ±4/6 Clock Generation Chip
MC100EL38DW	ONSEMI	获取价格	5V ECL ±2, ±4/6 Clock Generation Chip
MC100EL38DW	MOTOROLA	获取价格	±2, ±4/6 Clock Generation Chip
MC100EL38DWG	ONSEMI	获取价格	5V ECL ±2, ±4/6 Clock Generation Chip
MC100EL38DWR2	ONSEMI	获取价格	5V ECL ±2, ±4/6 Clock Generation Chip
MC100EL38DWR2	MOTOROLA	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, PLAST
MC100EL38DWR2G	ONSEMI	获取价格	5V ECL ±2, ±4/6 Clock Generation Chip
MC100EL39	MOTOROLA	获取价格	±2/4,±4/6 Clock Generation Chip
MC100EL39	ONSEMI	获取价格	±2/4, ±4/6 Clock Generation Chip
MC100EL39DW	MOTOROLA	获取价格	±2/4,±4/6 Clock Generation Chip

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