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MC100EL39DWR2G PDF预览

MC100EL39DWR2G

更新时间： 2024-11-02 05:22:27
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器时钟发生器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 121K
描述
5V ECL ±2/4, ±4/6 Clock Generation Chip

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中文翻译

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MC100EL39DWR2G 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP20,.4针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.73Is Samacsys：N
其他特性：NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V系列：100EL
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G20
JESD-609代码：e3长度：12.8 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER最大频率@ Nom-Sup：1000000000 Hz
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：20
实输出次数：4最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：+-5 V
最大电源电流（ICC）：61 mA传播延迟（tpd）：1.2 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：2.65 mm子类别：Prescaler/Multivibrators
最大供电电压 (Vsup)：5.7 V最小供电电压 (Vsup)：4.2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：7.5 mm
最小 fmax：1000 MHzBase Number Matches：1

MC100EL39DWR2G 数据手册

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MC100EL39  
5VꢀECL ÷2/4, ÷4/6 Clock  
Generation Chip  
The MC100EL39 is a low skew ÷2/4, ÷4/6 clock generation chip  
designed explicitly for low skew clock generation applications. The  
internal dividers are synchronous to each other, therefore, the common  
output edges are all precisely aligned.  
http://onsemi.com  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
BB  
The common enable (EN) is synchronous so that the internal  
dividers will only be enabled/disabled when the internal clock is  
already in the LOW state. This avoids any chance of generating a runt  
clock pulse on the internal clock when the device is enabled/disabled  
as can happen with an asynchronous control. An internal runt pulse  
could lead to losing synchronization between the internal divider  
stages. The internal enable flip-flop is clocked on the falling edge of  
the input clock, therefore, all associated specification limits are  
referenced to the negative edge of the clock input.  
Upon startup, the internal flip-flops will attain a random state;  
therefore, for systems which utilize multiple EL39s, the Master Reset  
(MR) input must be asserted to ensure synchronization. For systems  
which only use one EL39, the MR pin need not be exercised as the  
internal divider design ensures synchronization between the ÷2/4 and  
the ÷4/6 outputs of a single device.  
SO−20 WB  
DW SUFFIX  
CASE 751D  
MARKING DIAGRAM*  
20  
100EL39  
AWLYYWWG  
Features  
• 50 ps Output-to-Output Skew  
• Synchronous Enable/Disable  
1
• Master Reset for Synchronization  
• ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 100 V  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
WL  
YY  
WW  
G
• The 100 Series Contains Temperature Compensation  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V  
CC  
EE  
• NECL Mode Operating Range: V = 0 V with  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
V
= −4.2 V to −5.7 V  
EE  
• Internal Input Pulldown Resistors on EN, MR, CLK(s), and  
DIVSEL(s)  
• Q Output will Default LOW with Inputs Open or at V  
EE  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
• Moisture Sensitivity Level 1  
For Additional Information, see Application Note AND8003/D  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index 28 to 34  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
• Transistor Count = 419 devices  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 6  
MC100EL39/D  
1234567

中文翻译

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MC100EL39DWR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC100EL39DWR2 ONSEMI

完全替代

 5V ECL ±2/4, ±4/6 Clock Generation Chip
MC100EL39DWG ONSEMI

完全替代

 5V ECL ±2/4, ±4/6 Clock Generation Chip
MC100EL39DW ONSEMI

完全替代

 5V ECL ±2/4, ±4/6 Clock Generation Chip

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