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MC100EL52MNR4 PDF预览

MC100EL52MNR4

更新时间: 2024-02-20 13:56:20
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路时钟
页数 文件大小 规格书
9页 153K
描述
5V ECL Differential Data and Clock D Flip-Flop

MC100EL52MNR4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DFN
包装说明:HVSON, SOLCC8,.08,20针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.41Is Samacsys:N
其他特性:NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V系列:100EL
JESD-30 代码:S-XDSO-N8JESD-609代码:e3
长度:2 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:2200000000 Hz位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:UNSPECIFIED
封装代码:HVSON封装等效代码:SOLCC8,.08,20
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:-4.5 V最大电源电流(ICC):29 mA
Prop。Delay @ Nom-Sup:0.51 ns传播延迟(tpd):0.465 ns
认证状态:Not Qualified座面最大高度:1 mm
子类别:FF/Latches最大供电电压 (Vsup):5.7 V
最小供电电压 (Vsup):4.2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:2 mm
最小 fmax:2200 MHzBase Number Matches:1

MC100EL52MNR4 数据手册

 浏览型号MC100EL52MNR4的Datasheet PDF文件第2页浏览型号MC100EL52MNR4的Datasheet PDF文件第3页浏览型号MC100EL52MNR4的Datasheet PDF文件第4页浏览型号MC100EL52MNR4的Datasheet PDF文件第5页浏览型号MC100EL52MNR4的Datasheet PDF文件第6页浏览型号MC100EL52MNR4的Datasheet PDF文件第7页 
MC10EL52, MC100EL52  
5VꢀECL Differential Data  
and Clock D Flip-Flop  
Description  
The MC10EL/100EL52 is a differential data, differential clock D  
flip-flop with reset. The device is functionally equivalent to the E452  
device with higher performance capabilities. With propagation delays  
and output transition times significantly faster than the E452, the  
EL52 is ideally suited for those applications which require the ultimate  
in AC performance.  
Data enters the master portion of the flip-flop when the clock is  
LOW and is transferred to the slave, and thus the outputs, upon a  
positive transition of the clock. The differential clock inputs of the  
EL52 allow the device to also be used as a negative edge triggered  
device.  
http://onsemi.com  
MARKING  
DIAGRAMS*  
8
8
1
8
1
HEL52  
KEL52  
ALYW  
G
ALYW  
G
SOIC8  
D SUFFIX  
CASE 751  
1
The EL52 employs input clamping circuitry so that under open input  
conditions (pulled down to V ) the outputs of the device will remain  
stable.  
The 100 Series contains temperature compensation.  
EE  
8
1
8
8
1
HL52  
ALYWG  
G
KL52  
ALYWG  
G
TSSOP8  
DT SUFFIX  
CASE 948R  
Features  
1
365 ps Propagation Delay  
2.0 GHz Toggle Frequency  
ESD Protection: > 1 kV Human Body Model,  
> 100 V Machine Model  
PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
1
4
1
4
with V = 0 V  
EE  
DFN8  
MN SUFFIX  
CASE 506AA  
NECL Mode Operating Range: V = 0 V  
CC  
with V = 4.2 V to 5.7 V  
EE  
Internal Input Pulldown Resistors on D and CLK  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
Moisture Sensitivity Level 1  
For Additional Information, see Application Note AND8003/D  
Flammability Rating: UL 94 V0 @ 0.125 in,  
Oxygen: Index 28 to 34  
H = MC10  
L
Y
= Wafer Lot  
= Year  
K
= MC100  
4Y = MC10  
2N = MC100  
W = Work Week  
M = Date Code  
G
A
= Assembly Location  
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
Transistor Count = 48 devices  
PbFree Packages are Available  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 5  
MC10EL52/D  

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