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MC100EL51DTR2G PDF预览

MC100EL51DTR2G

更新时间: 2024-01-07 22:04:56
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
9页 152K
描述
5V ECL Differential Clock D Flip-Flop

MC100EL51DTR2G 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP, TSSOP8,.19针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.65
Is Samacsys:N其他特性:NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V
系列:100ELJESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:1800000000 Hz
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:-4.5 V
最大电源电流(ICC):36 mAProp。Delay @ Nom-Sup:0.62 ns
传播延迟(tpd):0.565 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.7 V最小供电电压 (Vsup):4.2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:3 mm最小 fmax:2200 MHz
Base Number Matches:1

MC100EL51DTR2G 数据手册

 浏览型号MC100EL51DTR2G的Datasheet PDF文件第2页浏览型号MC100EL51DTR2G的Datasheet PDF文件第3页浏览型号MC100EL51DTR2G的Datasheet PDF文件第4页浏览型号MC100EL51DTR2G的Datasheet PDF文件第5页浏览型号MC100EL51DTR2G的Datasheet PDF文件第6页浏览型号MC100EL51DTR2G的Datasheet PDF文件第7页 
MC10EL51, MC100EL51  
5VꢀECL Differential Clock D  
Flip-Flop  
Description  
The MC10EL/100EL51 is a differential clock D flip-flop with reset.  
The device is functionally similar to the E151 device with higher  
performance capabilities. With propagation delays and output  
transition times significantly faster than the E151 the EL51 is ideally  
suited for those applications which require the ultimate in AC  
performance.  
The reset input is an asynchronous, level triggered signal. Data  
enters the master portion of the flip-flop when the clock is LOW and is  
transferred to the slave, and thus the outputs, upon a positive transition  
of the clock. The differential clock inputs of the EL51 allow the device  
to be used as a negative edge triggered flip-flop.  
http://onsemi.com  
MARKING  
DIAGRAMS*  
8
8
1
8
1
HEL51  
KEL51  
ALYW  
G
ALYW  
G
SOIC8  
D SUFFIX  
CASE 751  
1
The differential input employs clamp circuitry to maintain stability  
under open input (pulled down to V ) conditions.  
The 100 Series contains temperature compensation.  
EE  
8
1
8
8
1
HL51  
ALYWG  
G
KL51  
ALYWG  
G
Features  
TSSOP8  
DT SUFFIX  
CASE 948R  
475 ps Propagation Delay  
2.8 GHz Toggle Frequency  
1
ESD Protection: > 1 kV Human Body Model,  
> 100 V Machine Model  
PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
1
4
1
4
NECL Mode Operating Range: V = 0 V  
CC  
DFN8  
MN SUFFIX  
CASE 506AA  
with V = 4.2 V to 5.7 V  
EE  
Internal Input Pulldown Resistors on D, R, and CLK  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
Moisture Sensitivity Level 1  
H = MC10  
L
= Wafer Lot  
K
= MC100  
Y = Year  
For Additional Information, see Application Note AND8003/D  
Flammability Rating: UL 94 V0 @ 0.125 in,  
Oxygen Index: 28 to 34  
Transistor Count = 73 devices  
PbFree Packages are Available  
4X = MC10  
2M= MC100  
W = Work Week  
M = Date Code  
A
= Assembly Location  
G
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 6  
MC10EL51/D  

MC100EL51DTR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC100EL51DTR2 ONSEMI

完全替代

5V ECL Differential Clock D Flip-Flop
MC100EL31DTG ONSEMI

类似代替

5 V ECL D Flip-Flop With Set and Reset
MC10EL31DTG ONSEMI

类似代替

5 V ECL D Flip-Flop With Set and Reset

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