MC100EL39DW

更新时间： 2024-02-23 19:31:50

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器时钟发生器逻辑集成电路光电二极管
页数	文件大小	规格书
4页	130K
描述
±2/4,±4/6 Clock Generation Chip

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中文翻译

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技术参数
数据手册

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MC100EL39DW 技术参数

是否无铅：	含铅	生命周期：	Active
零件包装代码：	SOIC	包装说明：	LEAD FREE, SOIC-20
针数：	20	Reach Compliance Code：	unknown
风险等级：	5.75	Is Samacsys：	N
其他特性：	NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V	系列：	100EL
输入调节：	DIFFERENTIAL	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e3	长度：	12.8 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	湿度敏感等级：	NOT SPECIFIED
功能数量：	1	反相输出次数：
端子数量：	20	实输出次数：	4
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	1.2 ns
认证状态：	COMMERCIAL	Same Edge Skew-Max（tskwd）：	0.05 ns
座面最大高度：	2.65 mm	最大供电电压 (Vsup)：	5.7 V
最小供电电压 (Vsup)：	4.2 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	7.5 mm	最小 fmax：	1000 MHz
Base Number Matches：	1

MC100EL39DW 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip

designed explicitly for low skew clock generation applications. The

MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but

is specified for operation at the standard 100K ECL voltage supply. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by either

a differential or single-ended LVECL or, if positive power supplies are

used, LVPECL input signal. In addition, by using the V

sinusoidal source can be AC coupled into the device (see Interfacing

section of the ECLinPS Data Book DL140/D). If a single-ended input is

output, a

to be used, the V

output should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. The V

output is designed to

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

act as the switching reference for the input of the LVEL39 under

single-ended input conditions, as a result, this pin can only source/sink up

to 0.5mA of current.

The common enable (EN) is synchronous so that the internal dividers

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen

with an asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip-flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

PIN DESCRIPTION

FUNCTION

CLK

Diff Clock Inputs

Sync Enable

Master Reset

Upon startup, the internal flip-flops will attain a random state; therefore,

for systems which utilize multiple LVEL39s, the master reset (MR) input

must be asserted to ensure synchronization. For systems which only use

one LVEL39, the MR pin need not be exercised as the internal divider

design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of

a single device.

Reference Output

Diff ÷2/4 Outputs

Diff ÷4/6 Outputs

Frequency Select Input

Q , Q

DIVSEL

FUNCTION TABLE

• 50ps Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• 75kΩ Internal Input Pulldown Resistors

• >2000V ESD Protection

CLK

FUNCTION

Divide

Hold Q

0–3

Reset Q

0–3

Z = Low-to-High Transition

ZZ = High-to-Low Transition

• Low Voltage V

Range of –3.0 to –3.8V

DIVSELa

Q , Q OUTPUTS

0 1

Pinout: 20-Lead SOIC (Top View)

Divide by 2

Divide by 4

DIVSELb

Q , Q OUTPUTS

2 3

Divide by 4

Divide by 6

EN DIVSELb CLK CLK

NC DIVSELa

3/96

Motorola, Inc. 1996

REV 2

4–1

12 3 4

中文翻译

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与MC100EL39DW相关器件

型号	品牌	获取价格	描述	数据表
MC100EL39DWG	ONSEMI	获取价格	5V ECL ±2/4, ±4/6 Clock Generation Chip
MC100EL39DWR2	ONSEMI	获取价格	5V ECL ±2/4, ±4/6 Clock Generation Chip
MC100EL39DWR2G	ONSEMI	获取价格	5V ECL ±2/4, ±4/6 Clock Generation Chip
MC100EL51	ONSEMI	获取价格	Differential Clock D Flip-Flop
MC100EL51D	MOTOROLA	获取价格	Differential Clock D Flip-Flop
MC100EL51D	ONSEMI	获取价格	5V ECL Differential Clock D Flip-Flop
MC100EL51DG	ONSEMI	获取价格	5V ECL Differential Clock D Flip-Flop
MC100EL51DR2	ONSEMI	获取价格	Differential Clock D Flip-Flop
MC100EL51DR2G	ONSEMI	获取价格	5V ECL Differential Clock D Flip-Flop
MC100EL51DT	ONSEMI	获取价格	5V ECL Differential Clock D Flip-Flop

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