Datasheet > SY100EL34

SY100EL34

更新时间： 2024-09-22 14:54:15

品牌	Logo	应用领域
美国微芯 - MICROCHIP		局域网（LAN）标准
页数	文件大小	规格书
14页	744K
描述
The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew

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SY100EL34 数据手册

SY100EL34/SY100EL34L

5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip

Features

General Description

• 3.3V (100EL34L) and 5V (100EL34) Power

Supply Options

The SY100EL34/SY100EL34L is a low skew ÷2, ÷4, ÷8

clock generation chip designed explicitly for low skew

clock generation applications. The internal dividers are

synchronous to each other; therefore, the common

output edges are all precisely aligned. The devices can

be driven by either a differential or single-ended ECL

or, if positive power supplies are used, PECL input

signal. In addition, by using the VBB output, a

sinusoidal source can be AC-coupled into the device. If

a single-ended input is to be used, the V_BBoutput

should be connected to the input and bypassed to

ground via a 0.01 µF capacitor. The VBB output is

designed to act as the switching reference for the input

of the 100EL34/100EL34L under single-ended input

conditions. As a result, this pin can only source/sink up

to 0.5 mA of current.

• 50 ps Output to Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• Internal 75 kΩ Input Pull Down Resistors

• Available in 16-Pin SOIC Package

Package Type

SY100EL34/SY100EL34L

16-Lead Narrow SOIC (Z16-2)

VCC

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the low state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop

is clocked on the falling edge of the divider stages. The

internal enable flip-flop is clocked on the falling edge of

the input clock; therefore, all associated specification

limits are referenced to the negative edge of the clock

input.

/Q0

/EN

VCC

/CLK

VBB

/Q1

VCC

/Q2

VEE

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple 100EL34/100EL34L in a system.

 2021 Microchip Technology Inc.

DS20006505A-page 1

12 3 4 5 6 7...14

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与SY100EL34相关器件

型号	品牌	获取价格	描述	数据表
SY100EL34L	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34LZC	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34LZC	MICROCHIP	获取价格	Low Skew Clock Driver, 100EL Series, 3 True Output(s), 0 Inverted Output(s), ECL, PDSO16
SY100EL34LZCTR	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34LZG	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34LZG	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL34LZGTR	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34LZG-TR	MICROCHIP	获取价格	100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL34LZI	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP
SY100EL34LZITR	MICREL	获取价格	5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP

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