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SY100EL34LZC PDF预览

SY100EL34LZC

更新时间： 2024-11-09 20:32:51
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 209K
描述
Low Skew Clock Driver, 100EL Series, 3 True Output(s), 0 Inverted Output(s), ECL, PDSO16

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SY100EL34LZC 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：0.150 INCH, SOIC-16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.35
Is Samacsys：N系列：100EL
输入调节：DIFFERENTIALJESD-30 代码：R-PDSO-G16
JESD-609代码：e0逻辑集成电路类型：LOW SKEW CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：16实输出次数：3
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：OPEN-EMITTER封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
电源：-3.3 V最大电源电流（ICC）：54 mA
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
子类别：Clock Drivers表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
Base Number Matches：1

SY100EL34LZC 数据手册

 浏览型号SY100EL34LZC的Datasheet PDF文件第2页浏览型号SY100EL34LZC的Datasheet PDF文件第3页浏览型号SY100EL34LZC的Datasheet PDF文件第4页浏览型号SY100EL34LZC的Datasheet PDF文件第5页浏览型号SY100EL34LZC的Datasheet PDF文件第6页浏览型号SY100EL34LZC的Datasheet PDF文件第7页 
NOT RECOMMENDED FOR NEW DESIGNS  
SY10EL34/L  
SY100EL34/L  
5V/3.3V ÷2, ÷4, ÷8 Clock Generation Chip  
Precision Edge®  
General Description  
The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock  
generation chips designed explicitly for low-skew clock  
generation applications. The internal dividers are  
synchronous to each other; therefore, the common output  
edges are all precisely aligned. The devices can be driven  
by either a differential or single-ended ECL or, if positive  
power supplies are used, PECL input signal. In addition,  
by using the VBB output, a sinusoidal source can be AC-  
coupled into the device. If a single-ended input is to be  
Precision Edge®  
Features  
• 3.3V and 5V power supply options  
• 50ps output-to-output skew  
• Synchronous enable/disable  
• Master Reset for synchronization  
• Internal 75KΩ input pull-down resistors  
• Available in 16-pin SOIC package  
used, the VBB output should be connected to the CLK  
input and bypassed to ground via a 0.01µF capacitor. The  
VBB output is designed to act as the switching reference for  
the input of the EL34/L under single-ended input  
conditions. As a result, this pin can only source/ sink up to  
0.5mA of current.  
Pin Description  
Pin Name Pin Function  
CLK  
Differential clock inputs.  
Synchronous enable.  
The common enable (EN ) is synchronous so that the  
internal dividers will only be enabled/disabled when the  
internal clock is already in the LOW state. This avoids any  
chance of generating a runt clock pulse on the internal  
clock when the device is enabled/disabled as can happen  
with an asynchronous control. An internal runt pulse could  
lead to losing synchronization between the internal divider  
stages. The internal enable flip-flop is clocked on the  
falling edge of the divider stages. The internal enable flip-  
flop is clocked on the falling edge of the input clock;  
therefore, all associated specification limits are referenced  
to the negative edge of the clock input.  
EN  
MR  
VBB  
Q0  
Master reset.  
Reference output.  
Differential ÷2 outputs.  
Differential ÷4 outputs.  
Differential ÷8 outputs.  
Q1  
Q2  
Upon start-up, the internal flip-flops will attain a random  
state; the master reset (MR) input allows for the  
synchronization of the internal dividers, as well as for  
multiple EL34/Ls in a system.  
Data sheets and support documentation can be found on  
Micrel’s web site at: www.micrel.com.  
Precision Edge is a registered trademark of Micrel, Inc.  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com  
M9999-120611-I  
December 2011  
hbwhelp@micrel.com or (408) 955-1690  
1234567

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SY100EL34LZC 替代型号

型号 品牌 替代类型 描述 数据表
SY10EL34ZG MICROCHIP

类似代替

 10EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL34LZG MICROCHIP

类似代替

 100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100EL34ZG MICROCHIP

类似代替

 100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

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