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SY100E417JCTR

更新时间： 2024-11-19 22:09:15
品牌 Logo 应用领域
麦瑞 - MICREL 锁存器接口集成电路
页数 文件大小 规格书
5页 76K
描述
QUINT LVPECL-TO-PECL OR PECL-TO-LVPECL TRANSLATOR

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中文翻译

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SY100E417JCTR 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：QCCJ, LDCC28,.5SQReach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.16Is Samacsys：N
最大延迟：0.68 ns接口集成电路类型：PECL TO LVPECL TRANSCEIVER
JESD-30 代码：S-PQCC-J28JESD-609代码：e0
长度：11.48 mm湿度敏感等级：1
位数：1功能数量：5
端子数量：28最高工作温度：85 °C
最低工作温度：输出锁存器或寄存器：NONE
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：240电源：3.3/5,5 V
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Level Translators最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：ECL
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn85Pb15)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：11.48 mmBase Number Matches：1

SY100E417JCTR 数据手册

 浏览型号SY100E417JCTR的Datasheet PDF文件第2页浏览型号SY100E417JCTR的Datasheet PDF文件第3页浏览型号SY100E417JCTR的Datasheet PDF文件第4页浏览型号SY100E417JCTR的Datasheet PDF文件第5页 
QUINT LVPECL-TO-PECL  
OR PECL-TO-LVPECL  
TRANSLATOR  
SY100E417  
DESCRIPTION  
FEATURES  
■ 3.3V and 5V power supplies required  
■ Also, supports LVPECL-to-PECL translation  
■ 500ps propagation delays  
The SY100E417 is a quint LVPECL-to-PECL translator.  
It can also be used as a quint PECL-to-LVPECL translator.  
The device receives standard PECL signals and translates  
them to differential LVPECL output signals (or vice versa).  
The SY100E417 can also be used as a differential line  
receiver for PECL-to-PECL or LVPECL-to-LVPECL signals.  
However, please note that for the latter we will need two  
different power supplies. Please refer to Function Table for  
more details.  
■ Fully differential design  
■ Differential line receiver capability  
■ Available in 28-pin PLCC package  
A VBB output is provided for interfacing single ended  
input signals. If a single ended input is to be used, the VBB  
output should be connected to the Dn input and the active  
signal will drive the Dn input. When used, the VBB should  
be bypassed to VCC via a 0.01µF capacitor. The VBB is  
designed to act as a switching reference for the SY100E417  
under single ended input conditions. As a result, the pin  
can only source/sink 0.5mA of current.  
To accomplish the PECL-to-LVPECL level translation,  
the SY100E417 requires three power rails. The VCC and  
VCC_VBB supply is to be connected to the standard PECL  
supply, the 3.3V supply is to be connected to the VCCO  
supply, and GND is connected to the system ground plane.  
Both the VCC and VCCO should be bypassed to ground with  
a 0.01µF capacitor.  
To accomplish the LVPECL-to-PECL level translation,  
the SY100E417 requires three power rails as well. The 5.0V  
supply is connected to the VCC and VCCO pins, 3.3V supply  
is connected to the VCC_VBB pin and GND is connected to  
the system ground plane. VCC_VBB is used to provide a  
proper VBB output level if a single ended input is used.  
VCC_VBB = 3.3V is only required for single-ended LVPECL  
input. For differential LVPECL input, VCC_VBB can be either  
3.3V or 5.0V.  
BLOCK DIAGRAM  
Q
Q
0
0
D
D
0
0
D
D
1
1
Q
Q
1
1
D
D
2
2
Q
Q
2
2
D
D
3
3
Q
Q
3
3
D
D
4
4
Q
Q
4
4
VBB  
Under open input conditions, the Dn input will be biased  
at a VCC/2 voltage level and the Dn input will be pulled to  
GND. This condition will force the "Qn" output low, ensuring  
stability.  
FUNCTION TABLE  
Function  
Vcc  
5.0V  
5.0V  
5.0V  
5.0V  
Vcco  
3.3V  
5.0V  
5.0V  
3.3V  
Vcc_VBB  
5.0V  
PECL-to-LVPECL  
LVPECL-to-PECL  
PECL-to-PECL  
3.3V  
5.0V  
LVPECL-to-LVPECL  
3.3V  
Rev.: B  
Amendment:/1  
Issue Date: March, 1999  
1
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中文翻译

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