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SY100E431JC PDF预览

SY100E431JC

更新时间: 2024-02-24 14:26:47
品牌 Logo 应用领域
麦瑞 - MICREL 触发器锁存器逻辑集成电路
页数 文件大小 规格书
4页 64K
描述
3-BIT DIFFERENTIAL FLIP-FLOP

SY100E431JC 技术参数

生命周期:Active包装说明:QCCJ,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.66系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:D FLIP-FLOP
位数:1功能数量:3
端子数量:28最高工作温度:85 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):0.8 ns认证状态:Not Qualified
座面最大高度:4.57 mm表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
触发器类型:POSITIVE EDGE宽度:11.48 mm
最小 fmax:1100 MHzBase Number Matches:1

SY100E431JC 数据手册

 浏览型号SY100E431JC的Datasheet PDF文件第2页浏览型号SY100E431JC的Datasheet PDF文件第3页浏览型号SY100E431JC的Datasheet PDF文件第4页 
3-BIT DIFFERENTIAL  
FLIP-FLOP  
SY10E431  
SY100E431  
DESCRIPTION  
FEATURES  
Differential D, clock and Q  
The SY10/100E431 are 3-bit flip-flops with differential  
clock, data input and data output.  
Extended 100E VEE range of –4.2V to –5.5V  
VBB output for single-ended use  
The asynchronous Set and Reset controls are edge-  
triggered rather than level controlled. This allows the user  
to rapidly set or reset the flip-flop and then continue  
clocking at the next clock edge without the necessity of  
de-asserting the set/reset signal (as would be the case  
with a level controlled set/reset).  
The E431 is also designed with larger internal swings,  
an approach intended to minimize the time spent crossing  
the threshold region and thus reduces the metastability  
susceptibility window.  
1100MHz min. toggle frequency  
Edge-triggered asynchronous set and reset  
Fully compatible with Motorola MC10E/100E431  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
S0  
PIN CONFIGURATION  
S
R
D
D
0
0
D
D
D
Q
Q
Q
Q
0
0
CLK  
CLK  
0
0
R
0
25  
24 23 22 21 20 19  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
CLK1  
CLK1  
R1  
Q2  
Q2  
VCC  
Q1  
Q1  
Q0  
Q0  
S
1
S
R
D
D
1
1
Q
Q
Q
Q
1
1
TOP VIEW  
PLCC  
VEE  
S1  
J28-1  
CLK  
CLK  
1
1
2
3
D1  
4
D1  
R
1
5
6
7
8
9
10 11  
S
2
S
R
D
D
2
2
Q
Q
Q
Q
2
2
CLK  
CLK  
2
2
R
2
PIN NAMES  
V
BB  
Pin  
D[0:2], D[0:2]  
CLK[0:2], CLK[0:2]  
S[0:2]  
Function  
Differential Data Inputs  
Differential Clock Inputs  
Edge Triggered Set Inputs  
(1)  
TRUTH TABLE  
Dn  
L
CLKn  
Rn  
L
Sn  
Qn  
L
R[0:2]  
Edge Triggered Reset Inputs  
VBB Reference Output  
Differential Data Outputs  
VCC to Output  
Z
Z
L
L
L
L
L
Z
VBB  
H
X
L
H
L
Q[0:2], Q[0:2]  
VCCO  
Z
X
L
H
NOTE:  
1. Z = LOW-to-HIGH transition.  
Rev.: C  
Amendment:/1  
Issue Date: February, 1998  
1

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