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STU2071FN

更新时间： 2024-11-22 22:21:15

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		数字传输接口电信集成电路电信电路综合业务数字网
页数	文件大小	规格书
18页	281K
描述
4B3T U INTERFACE CIRCUIT

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中文翻译

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技术参数
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STU2071FN 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QLCC	包装说明：	PLASTIC, LCC-28
针数：	28	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.88
Is Samacsys：	N	数据速率：	144 Mbps
ISDN访问速率：	BASIC	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e0	长度：	11.5062 mm
功能数量：	1	端子数量：	28
最小输出高电压：	4 V	最大输出低电流：	0.0007 A
最大输出低电压：	0.4 V	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	5 V	认证状态：	Not Qualified
参照点：	U	座面最大高度：	4.57 mm
标准：	CCITT V.29	子类别：	Digital Transmission Interfaces
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	DIGITAL SLIC
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.5062 mm	Base Number Matches：	1

STU2071FN 数据手册

STU2071

4B3T U INTERFACE CIRCUIT

PRELIMINARY DATA

4B3T TWO-WIRE U INTERFACE CIRCUIT

FOR LT AND NT APPLICATION

120 kbaud LINE SYMBOL RATE (120 SYM-

BOLS PER FRAME)

SCRAMBLER AND DESCRAMBLER AC-

CORDING TO CCITT REC V.29

BARKER CODE (11 SYMBOLS) SYNCHRO-

NIZATION WORD

UNSCRAMBLED 1 KBIT/S HOUSEKEEPING

CHANNEL

ADAPTIVE ECHO CANCELLATION WITH

TRANSVERSAL FILTERING

DIP28

ADAPTIVE DECISION FEEDBACK EQUALI-

ZATION

ORDERING NUMBER: STU2071B1

AUTOMATIC GAIN CONTROL

PDM AD CONVERTER

AUTOMATIC ACTIVATION AND DEACTIVA-

TION WITH POLARITY ADAPTION

AUTOMATIC CODE VIOLATION DETECTION

POWER FEED UNIT CONTROL

ADVANCED CL3 1.5µm CMOS PROCESS

28 PIN DUAL-IN-LINE PLASTIC PACKAGE

V* DIGITAL INTERFACE

PLCC28

ORDERING NUMBER: STU2071FN

SYSTEM OVERVIEW

STU2071 (UIC) provides two transparent 64 kbit/s

B channels, a transparent 16 kbit/s D channel, a

transparent 1 kbit/s service channel and a 1 kbit/s

maintenance channel for loop and error mes-

sages on subscriber lines.

UIC enables full duplex continuous data transmis-

sion via the standard twisted pair telephone ca-

ble. Adaptive Echo cancellation is used to restore

the received data. An equalizer, done with an

adaptive filter, restores the data which are dis-

torted by the transmission line.

pass through a digital filter (TX-filter) to reduce

the high frequency components. After D/A con-

version the signal is amplified and sent to the hy-

brid.

The received signal is converted back to digital

data and passed through the RX matching filter to

restore the line signal. The A/D convertor is a

second order sigma/delta modulator which oper-

ates with a clock of 15.36 MHz. After timing re-

covery, achieved by a digital PLL, the received

signal is equalized, in an adaptive digital filter, to

correct for the frequency and group delay distor-

tion of the line.

The coefficient of the equalizer and echo cancel-

ler are conserved during a power down. An all

digital PLL performs both bit and frame synchroni-

zation.

The analog front end consists of receive path RX

and transmit path TX, providing a full duplex ana-

log interfacing to the twisted pair telephone cable.

Before data are converted to analog signals, they

Power supply status can be read via PFOFF. The

UIC can disable its power supply (DISS), and two

relay drivers outputs are provided (accessible via

B2*) to control the power feed unit (RD1,RD2).

September 1994

1/18

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

12 3 4 5 6 7...18

中文翻译

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