STP21N05L

更新时间： 2024-11-22 22:42:39

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		晶体晶体管
页数	文件大小	规格书
10页	199K
描述
N - CHANNEL ENHANCEMENT MODE LOW THRESHOLD POWER MOS TRANSISTOR

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中文翻译

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数据手册

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STP21N05L 数据手册

STP21N05L

STP21N05LFI

N - CHANNEL ENHANCEMENT MODE

LOW THRESHOLD POWER MOS TRANSISTOR

TYPE

V_DSS

R_DS(on)

I_D

STP21N05L

STP21N05LFI

50 V

< 0.085 Ω

21 A

14 A

■

TYPICAL R_DS(on)= 0.065 Ω

AVALANCHE RUGGED TECHNOLOGY

100% AVALANCHE TESTED

REPETITIVE AVALANCHE DATA AT 100^oC

LOW GATE CHARGE

LOGIC LEVEL COMPATIBLE INPUT

175 ^oC OPERATING TEMPERATURE

APPLICATION ORIENTED

TO-220

ISOWATT220

CHARACTERIZATION

APPLICATIONS

■

HIGH CURRENT, HIGH SPEED SWITCHING

SOLENOID AND RELAY DRIVERS

REGULATORS

DC-DC & DC-AC CONVERTERS

MOTOR CONTROL, AUDIO AMPLIFIERS

AUTOMOTIVE ENVIRONMENT (INJECTION,

ABS, AIR-BAG, LAMPDRIVERS, Etc.)

INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

STP21N05L

STP21N05LFI

V_DS

V_{DG R}

V_GS

I_D

Drain-source Voltage (V_GS= 0)

Drain- gate Voltage (R_GS= 20 kΩ)

Gate-source Voltage

Drain Current (continuous) at T_c= 25 ^oC

Drain Current (continuous) at T_c= 100 ^oC

Drain Current (pulsed)

± 15

I_D

I_DM(•)

P_tot

Total Dissipation at T_c= 25 ^oC

W/^oC

^oC

Derating Factor

0.53

0.23

2000

V_ISO

T_stg

T_j

Insulation Withstand Voltage (DC)

Storage Temperature

-65 to 175

175

Max. Operating Junction Temperature

(•) Pulse width limited by safe operating area

1/10

July 1993

12 3 4 5 6 7...10

中文翻译

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