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SSTUB32866EC/G,518

更新时间： 2024-02-03 05:21:16
品牌 Logo 应用领域
恩智浦 - NXP 双倍数据速率逻辑集成电路触发器
页数 文件大小 规格书
30页 236K
描述
SSTUB32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications BGA 96-Pin

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SSTUB32866EC/G,518 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LFBGA, BGA96,6X16,32
针数：96Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.84
系列：32866JESD-30 代码：R-PBGA-B96
长度：13.5 mm逻辑集成电路类型：D FLIP-FLOP
湿度敏感等级：2位数：25
功能数量：1端子数量：96
最高工作温度：70 °C最低工作温度：
输出特性：OPEN-DRAIN输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA96,6X16,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.8 V传播延迟（tpd）：1.5 ns
认证状态：Not Qualified座面最大高度：1.5 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30触发器类型：POSITIVE EDGE
宽度：5.5 mm最小 fmax：450 MHz
Base Number Matches：1

SSTUB32866EC/G,518 数据手册

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SSTUB32866  
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer  
with parity for DDR2-800 RDIMM applications  
Rev. 04 — 15 April 2010  
Product data sheet  
1. General description  
The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2  
memory modules requiring a parity checking function. The register is configurable (using  
configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter  
configuration can be designated as Register A or Register B on the DIMM.  
The SSTUB32866 accepts a parity bit from the memory controller on its parity bit  
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs  
and indicates whether a parity error has occurred on its open-drain QERR pin  
(active LOW). The convention is even parity, that is, valid parity is defined as an even  
number of ones across the DIMM-independent data inputs combined with the parity input  
bit.  
The SSTUB32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package  
(13.5 mm × 5.5 mm).  
2. Features and benefits  
„ Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications  
„ Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode  
„ Controlled output impedance drivers enable optimal signal integrity and speed  
„ Meets or exceeds SSTUB32866 JEDEC standard speed performance  
„ Supports up to 450 MHz clock frequency of operation  
„ Optimized pinout for high-density DDR2 module design  
„ Chip-selects minimize power consumption by gating data outputs from changing state  
„ Supports SSTL_18 data inputs  
„ Checks parity on the DIMM-independent data inputs  
„ Partial parity output and input allows cascading of two SSTUB32866s for correct parity  
error processing  
„ Differential clock (CK and CK) inputs  
„ Supports LVCMOS switching levels on the control and RESET inputs  
„ Single 1.8 V supply operation (1.7 V to 2.0 V)  
„ Available in 96-ball, 13.5 mm × 5.5 mm, 0.8 mm ball pitch LFBGA package  
3. Applications  
„ 400 MT/s to 800 MT/s DDR2 registered DIMMs desiring parity checking functionality  
 
 
 
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