Datasheet > SSTUG32865ET/G

SSTUG32865ET/G

更新时间： 2024-11-02 20:39:47

品牌	Logo	应用领域
恩智浦 - NXP		输出元件逻辑集成电路触发器
页数	文件大小	规格书
28页	141K
描述
IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160, 9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160, FF/Latch

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技术参数
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SSTUG32865ET/G 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160
针数：	160	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.84
系列：	SSTU	JESD-30 代码：	R-PBGA-B160
长度：	13 mm	逻辑集成电路类型：	D FLIP-FLOP
湿度敏感等级：	2	位数：	28
功能数量：	1	端子数量：	160
最高工作温度：	70 °C	最低工作温度：
输出特性：	OPEN-DRAIN	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	1.4 ns
认证状态：	Not Qualified	座面最大高度：	1.15 mm
最大供电电压 (Vsup)：	2 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	0.65 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	触发器类型：	POSITIVE EDGE
宽度：	9 mm	最小 fmax：	550 MHz
Base Number Matches：	1

SSTUG32865ET/G 数据手册

SSTUG32865

1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-1G

RDIMM applications

Rev. 01 — 16 August 2007

Product data sheet

1. General description

The SSTUG32865 is a 1.8 V 28-bit 1 : 2 register speciﬁcally designed for use on two rank

by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It

is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the

functionality of the normally required two registers in a single package, thereby freeing up

board real-estate and facilitating routing to accommodate high-density Dual In-line

Memory Module (DIMM) designs.

The SSTUG32865 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

It further offers added features over the JEDEC standard register in that it can be

conﬁgured for normal or high output drive strength, simply by tying input pin SELDR either

HIGH of LOW as needed. This allows use in different module designs varying from low to

high density designs by picking the appropriate drive strength to match net loading

conditions. Furthermore, the SSTUG32865 features two additional chip select inputs,

which allow more versatile enabling and disabling in densely populated memory modules.

Both added features (drive strength and chip selects) are fully backward compatible to the

JEDEC standard register.

The SSTUG32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin proﬁle

ﬁne-pitch ball grid array (TFBGA) package, which, while requiring a minimum

9 mm × 13 mm of board space, allows for adequate signal routing and escape using

conventional card technology.

2. Features

I 28-bit data register supporting DDR2

I Fully compliant to JEDEC standard for SSTUB32865

I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2 × SSTUB32864 or 2 × SSTUB32866)

I Parity checking function across 22 input data bits

I Parity out signal

I Controlled multi-impedance output impedance drivers enable optimal signal integrity

and speed

I Exceeds SSTUB32865 JEDEC standard speed performance

I Supports up to 550 MHz clock frequency of operation

I Programmable for normal or high output drive

I Optimized pinout for high-density DDR2 module design

12 3 4 5 6 7...28

中文翻译

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与SSTUG32865ET/G相关器件

型号	品牌	获取价格	描述	数据表
SSTUG32865ET/G,518	NXP	获取价格	SSTUG32865 - 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32865ET/S	NXP	获取价格	IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160, 9 X 13 MM, 0.70
SSTUG32866	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/G	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/G,518	NXP	获取价格	SSTUG32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUG32866EC/S	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/S,518	NXP	获取价格	SSTUG32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUG32868	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32868ET	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32868ET/G,518	NXP	获取价格	SSTUG32868 - 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDI

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