Datasheet > SSTUG32866

SSTUG32866

更新时间： 2024-11-02 06:14:23

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
28页	151K
描述
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer

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SSTUG32866 数据手册

SSTUG32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer

with parity for DDR2-1G RDIMM applications

Rev. 01 — 29 June 2007

Product data sheet

1. General description

The SSTUG32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2

memory modules requiring a parity checking function. It is deﬁned in accordance with the

JEDEC standard for the SSTUG32866 registered buffer. The register is conﬁgurable

(using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in

the latter conﬁguration can be designated as Register A or Register B on the DIMM.

The SSTUG32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is deﬁned as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

The SSTUG32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA

package (13.5 mm × 5.5 mm).

2. Features

I Conﬁgurable register supporting DDR2 up to 800 MT/s Registered DIMM applications

I Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

I Controlled output impedance drivers enable optimal signal integrity and speed

I Meets or exceeds SSTUG32866 JEDEC standard speed performance

I Supports up to 550 MHz clock frequency of operation

I Optimized pinout for high-density DDR2 module design

I Chip-selects minimize power consumption by gating data outputs from changing state

I Supports SSTL_18 data inputs

I Checks parity on the DIMM-independent data inputs

I Partial parity output and input allows cascading of two SSTUG32866s for correct parity

error processing

I Differential clock (CK and CK) inputs

I Supports LVCMOS switching levels on the control and RESET inputs

I Single 1.8 V supply operation (1.7 V to 2.0 V)

I Available in 96-ball, 13.5 mm × 5.5 mm, 0.8 mm ball pitch LFBGA package

3. Applications

I 400 MT/s to 800 MT/s and higher DDR2 registered DIMMs desiring parity checking

functionality

12 3 4 5 6 7...28

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与SSTUG32866相关器件

型号	品牌	获取价格	描述	数据表
SSTUG32866EC/G	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/G,518	NXP	获取价格	SSTUG32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUG32866EC/S	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/S,518	NXP	获取价格	SSTUG32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUG32868	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32868ET	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32868ET/G,518	NXP	获取价格	SSTUG32868 - 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDI
SSTUG32868ET/S,518	NXP	获取价格	SSTUG32868 - 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDI
SSTUG32868ETS	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32868G	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio

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