Datasheet > SSTUH32865

SSTUH32865

更新时间： 2024-09-28 06:14:23

品牌	Logo	应用领域
恩智浦 - NXP		驱动双倍数据速率
页数	文件大小	规格书
28页	143K
描述
1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applications

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SSTUH32865 数据手册

SSTUH32865

1.8 V 28-bit high output drive 1:2 registered buffer with parity

for DDR2 RDIMM applications

Rev. 01 — 11 March 2005

Product data sheet

1. General description

The SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register speciﬁcally designed for

use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2)

memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but

integrates the functionality of the normally required two registers in a single package,

thereby freeing up board real-estate and facilitating routing to accommodate high-density

Dual In-line Memory Module (DIMM) designs.

The SSTUH32865 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

The SSTUH32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin proﬁle

ﬁne-pitch ball grid array (TFBGA) package, which—while requiring a minimum

9 mm × 13 mm of board space—allows for adequate signal routing and escape using

conventional card technology.

The SSTUH32865 is identical to SSTU32865 in function and performance, with

higher-drive outputs optimized to drive heavy load nets (such as stacked DRAMs) while

maintaining speed and signal integrity.

2. Features

■ 28-bit data register supporting DDR2

■ Higher output drive strength version of SSTU32865 optimized for high-capacitive load

nets

■ Fully compliant to JEDEC standard JESD82-9

■ Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2 × SSTU32864 or 2 × SSTU32866)

■ Parity checking function across 22 input data bits

■ Parity out signal

■ Controlled output impedance drivers enable optimal signal integrity and speed

■ Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation

delay, 2.0 ns max. mass-switching)

■ Supports up to 450 MHz clock frequency of operation

■ Optimized pinout for high-density DDR2 module design

■ Chip-selects minimize power consumption by gating data outputs from changing state

■ Supports Stub Series Terminated Logic SSTL_18 data inputs

■ Differential clock (CK and CK) inputs

12 3 4 5 6 7...28

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与SSTUH32865相关器件

型号	品牌	获取价格	描述	数据表
SSTUH32865ET	NXP	获取价格	1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applicatio
SSTUH32865ET,518	NXP	获取价格	SSTUH32865 - 1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDI
SSTUH32865ET,551	NXP	获取价格	SSTUH32865 - 1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDI
SSTUH32865ET/G	NXP	获取价格	1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applicatio
SSTUH32865ET/G,551	NXP	获取价格	SSTUH32865 - 1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDI
SSTUH32866	NXP	获取价格	1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with p
SSTUH32866EC	NXP	获取价格	1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with p
SSTUH32866EC/G	NXP	获取价格	1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with p
SST-ULD-S1	DOMINANT	获取价格	SpiceLED InGaN S-Spice
SST-ULD-S2	DOMINANT	获取价格	SpiceLED InGaN S-Spice

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