SSTUM32865ETS

更新时间： 2024-01-29 16:13:20

品牌	Logo	应用领域
恩智浦 - NXP		双倍数据速率
页数	文件大小	规格书
28页	153K
描述
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

SSTUM32865ETS 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	9 X 13 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, SOT-802-2, TFBGA-160
针数：	160	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.84
系列：	SSTU	JESD-30 代码：	R-PBGA-B160
长度：	13 mm	逻辑集成电路类型：	D FLIP-FLOP
湿度敏感等级：	2	位数：	28
功能数量：	1	端子数量：	160
最高工作温度：	85 °C	最低工作温度：
输出特性：	OPEN-DRAIN	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装等效代码：	BGA160,12X18,25	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
电源：	1.8 V	传播延迟（tpd）：	1.4 ns
认证状态：	Not Qualified	座面最大高度：	1.15 mm
子类别：	Other Logic ICs	最大供电电压 (Vsup)：	2 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	温度等级：	OTHER
端子形式：	BALL	端子节距：	0.65 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
触发器类型：	POSITIVE EDGE	宽度：	9 mm
最小 fmax：	450 MHz	Base Number Matches：	1

SSTUM32865ETS 数据手册

SSTUM32865

1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800

RDIMM applications

Rev. 01 — 19 September 2007

Product data sheet

1. General description

The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register speciﬁcally designed for use on two rank

by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It

is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the

functionality of the normally required two registers in a single package, thereby freeing up

board real-estate and facilitating routing to accommodate high-density Dual In-line

Memory Module (DIMM) designs.

The SSTUM32865 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

It further offers added features over the JEDEC standard register in that it is permanently

conﬁgured for high output drive strength. This allows use in high density designs with

heavier than normal net loading conditions. Furthermore, the SSTUM32865 features two

additional chip select inputs, which allow more versatile enabling and disabling in densely

populated memory modules. Both added features (drive strength and chip selects) are

fully backward compatible to the JEDEC standard register.

The SSTUM32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin proﬁle

ﬁne-pitch ball grid array (TFBGA) package, which, while requiring a minimum

9 mm × 13 mm of board space, allows for adequate signal routing and escape using

conventional card technology.

2. Features

I 28-bit data register supporting DDR2

I Fully compliant to JEDEC standard for SSTUB32865

I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2 × SSTUB32864 or 2 × SSTUB32866)

I Parity checking function across 22 input data bits

I Parity out signal

I Controlled multi-impedance output impedance drivers enable optimal signal integrity

and speed

I Meets or exceeds SSTUB32865 JEDEC standard speed performance

I Supports up to 450 MHz clock frequency of operation

I Permanently conﬁgured for high output drive

I Optimized pinout for high-density DDR2 module design

I Chip-selects minimize power consumption by gating data outputs from changing state

I Two additional chip select inputs allow optional ﬂexible enabling and disabling

12 3 4 5 6 7...28

中文翻译

下载PDF

与SSTUM32865ETS相关器件

型号	品牌	获取价格	描述	数据表
SSTUM32866	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G
SSTUM32866EC/G	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G
SSTUM32866EC/G,518	NXP	获取价格	SSTUM32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUM32866EC/S	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G
SSTUM32868	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applicati
SSTUM32868ET,518	NXP	获取价格	SSTUM32868 - 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RD
SSTUM32868ET/G	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applicati
SSTUM32868ET/G,518	NXP	获取价格	IC,MEMORY DRIVER,BGA,176PIN,PLASTIC
SSTUM32868ET/S	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applicati
SSTUM32868ET/S,518	NXP	获取价格	SSTUM32868 - 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RD

与SSTUM32865ETS相关文章

BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

3
解读EGP10B二极管资料手册：产品特性、参数分析
2024-07-04

3
RT9164AGG手册资料详解：引脚信息、设计指南
2024-07-04

3
2SA1037KPT资料详解：产品特性、电气参数、设计指南
2024-07-04

3

产品中心

服务支持

精选活动

关于我们

帮助中心

SSTUM32865ETS

SSTUM32865ETS 技术参数

SSTUM32865ETS 数据手册

与SSTUM32865ETS相关器件

与SSTUM32865ETS相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SSTUM32865ETS

SSTUM32865ETS 技术参数

SSTUM32865ETS 数据手册

与SSTUM32865ETS相关器件

与SSTUM32865ETS相关文章

您还可以找

您在本页遇到什么问题？