Datasheet > SSTUM32866EC/G,518

SSTUM32866EC/G,518

更新时间： 2024-01-01 09:29:36

品牌	Logo	应用领域
恩智浦 - NXP		驱动双倍数据速率逻辑集成电路
页数	文件大小	规格书
28页	138K
描述
SSTUM32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications BGA 96-Pin

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SSTUM32866EC/G,518 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	针数：	96
Reach Compliance Code：	unknown	风险等级：	5.84
Is Samacsys：	N	JESD-30 代码：	R-PBGA-B96
逻辑集成电路类型：	BUS DRIVER	端子数量：	96
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	FBGA
封装等效代码：	BGA96,6X16,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, FINE PITCH	电源：	1.8 V
认证状态：	Not Qualified	子类别：	Other Logic ICs
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
Base Number Matches：	1

SSTUM32866EC/G,518 数据手册

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SSTUM32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer

with parity for DDR2-1G RDIMM applications

Rev. 01 — 29 June 2007

Product data sheet

1. General description

The SSTUM32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2

memory modules requiring a parity checking function. It is deﬁned in accordance with the

JEDEC standard for the SSTUM32866 registered buffer. The register is conﬁgurable

(using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in

the latter conﬁguration can be designated as Register A or Register B on the DIMM.

The SSTUM32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is deﬁned as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

The SSTUM32866 is the high-output drive version of SSTUG32866.

The SSTUM32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA

package (13.5 mm × 5.5 mm).

2. Features

I Conﬁgurable register supporting DDR2 up to 800 MT/s Registered DIMM applications

I Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

I Controlled output impedance drivers enable optimal signal integrity and speed

I Meets or exceeds SSTUM32866 JEDEC standard speed performance

I High output drive

I Supports up to 550 MHz clock frequency of operation

I Optimized pinout for high-density DDR2 module design

I Chip-selects minimize power consumption by gating data outputs from changing state

I Supports SSTL_18 data inputs

I Checks parity on the DIMM-independent data inputs

I Partial parity output and input allows cascading of two SSTUM32866s for correct parity

error processing

I Differential clock (CK and CK) inputs

I Supports LVCMOS switching levels on the control and RESET inputs

I Single 1.8 V supply operation (1.7 V to 2.0 V)

I Available in 96-ball, 13.5 mm × 5.5 mm, 0.8 mm ball pitch LFBGA package

12 3 4 5 6 7...28

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与SSTUM32866EC/G,518相关器件

型号	品牌	获取价格	描述	数据表
SSTUM32866EC/S	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G
SSTUM32868	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applicati
SSTUM32868ET,518	NXP	获取价格	SSTUM32868 - 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RD
SSTUM32868ET/G	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applicati
SSTUM32868ET/G,518	NXP	获取价格	IC,MEMORY DRIVER,BGA,176PIN,PLASTIC
SSTUM32868ET/S	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applicati
SSTUM32868ET/S,518	NXP	获取价格	SSTUM32868 - 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RD
SSTUP32866	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programm
SSTUP32866EC/G	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programm
SSTUP32866EC/S	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programm

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