Datasheet > SSTUP32866EC/S

SSTUP32866EC/S

更新时间： 2024-01-22 14:34:38

品牌	Logo	应用领域
恩智浦 - NXP		双倍数据速率
页数	文件大小	规格书
31页	542K
描述
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity and programmable output for DDR2-800 RDIMMs

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技术参数
数据手册

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SSTUP32866EC/S 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LFBGA, BGA96,6X16,32
针数：	96	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.84
系列：	32866	JESD-30 代码：	R-PBGA-B96
JESD-609代码：	e1	长度：	13.5 mm
逻辑集成电路类型：	D FLIP-FLOP	位数：	25
功能数量：	1	端子数量：	96
最高工作温度：	85 °C	最低工作温度：
输出特性：	OPEN-DRAIN	输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	BGA96,6X16,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	电源：	1.8 V
传播延迟（tpd）：	1.8 ns	认证状态：	Not Qualified
座面最大高度：	1.5 mm	子类别：	Other Logic ICs
最大供电电压 (Vsup)：	2 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL EXTENDED
端子面层：	TIN SILVER COPPER	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
触发器类型：	POSITIVE EDGE	宽度：	5.5 mm
最小 fmax：	450 MHz	Base Number Matches：	1

SSTUP32866EC/S 数据手册

SSTUP32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer

with parity and programmable output for DDR2-800 RDIMMs

Rev. 02 — 14 September 2006

Product data sheet

1. General description

The SSTUP32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2

memory modules requiring a parity checking function. It is deﬁned in accordance with the

JEDEC standard for the SSTUA32866 and SSTUB32866 registered buffers. The register

is conﬁgurable (using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or

14-bit 1 : 2, and in the latter conﬁguration can be designated as Register A or Register B

on the DIMM. It offers added features over the JEDEC standard register in that it can be

conﬁgured for high or normal output drive strength, as well as for operation to 667 MT/s or

800 MT/s, simply by tying two input pins HIGH or LOW as needed.

The SSTUP32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is deﬁned as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

The SSTUP32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA

package (13.5 mm × 5.5 mm).

2. Features

I Conﬁgurable register supporting DDR2 up to 667 MT/s or 800 MT/s Registered DIMM

applications

I Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

I Programmable for normal or high output drive

I Controlled multi-impedance output drivers enable optimal signal integrity and speed

I Programmable for 667 MT/s or 800 MT/s speed

I Excellent propagation delay performance

I Supports up to 450 MHz clock frequency of operation

I Optimized pinout for high-density DDR2 module design

I Chip-selects minimize power consumption by gating data outputs from changing state

I Supports SSTL_18 data inputs

I Checks parity on the DIMM-independent data inputs

I Partial parity output and input allows cascading of two SSTUP32866s for correct parity

error processing

I Differential clock (CK and CK) inputs

I Supports LVCMOS switching levels on the control and RESET inputs

I Single 1.8 V supply operation (1.7 V to 2.0 V)

12 3 4 5 6 7...31

中文翻译

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与SSTUP32866EC/S相关器件

型号	品牌	获取价格	描述	数据表
SSTV16857	FAIRCHILD	获取价格	14-Bit Register with SSTL-2 Compatible I/O and Reset
SSTV16857	NXP	获取价格	14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857CG	IDT	获取价格	TSSOP-48, Tube
SSTV16857CG-T	IDT	获取价格	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 6.
SSTV16857DGG	NXP	获取价格	14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857DGG	PHILIPS	获取价格	Bus Driver, PDSO48
SSTV16857DGG,112	NXP	获取价格	SSTV16857 - 14-bit SSTL_2 registered driver with differential clock inputs TSSOP 48-Pin
SSTV16857DGG,118	NXP	获取价格	SSTV16857 - 14-bit SSTL_2 registered driver with differential clock inputs TSSOP 48-Pin
SSTV16857DGG,512	NXP	获取价格	SSTV16857 - 14-bit SSTL_2 registered driver with differential clock inputs TSSOP 48-Pin
SSTV16857DGG,518	NXP	获取价格	SSTV16857 - 14-bit SSTL_2 registered driver with differential clock inputs TSSOP 48-Pin

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