Datasheet > SSTUH32866EC/G

SSTUH32866EC/G

更新时间： 2024-01-07 09:05:14

品牌	Logo	应用领域
恩智浦 - NXP		驱动双倍数据速率
页数	文件大小	规格书
28页	146K
描述
1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applications

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SSTUH32866EC/G 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	FBGA, BGA96,6X16,32	Reach Compliance Code：	unknown
风险等级：	5.7	JESD-30 代码：	R-PBGA-B96
逻辑集成电路类型：	BUS DRIVER	端子数量：	96
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	FBGA
封装等效代码：	BGA96,6X16,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, FINE PITCH	电源：	1.8 V
认证状态：	Not Qualified	子类别：	Other Logic ICs
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	Base Number Matches：	1

SSTUH32866EC/G 数据手册

SSTUH32866

1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable

registered buffer with parity for DDR2 RDIMM applications

Rev. 01 — 13 May 2005

Product data sheet

1. General description

The SSTUH32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2

memory modules requiring a parity checking function. It is deﬁned in accordance with the

JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity

checking function in a compatible pinout. The JEDEC standard for SSTUH32866 is

pending publication. The register is conﬁgurable (using conﬁguration pins C0 and C1) to

two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter conﬁguration can be designated

as Register A or Register B on the DIMM.

The SSTUH32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is deﬁned as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

The SSTUH32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA

package (13.5 mm × 5.5 mm).

The SSTUH32866 is identical to SSTU32866 in function and performance, with

higher-drive outputs optimized to drive heavy load nets (for example, stacked DRAMs)

while maintaining speed and signal integrity.

2. Features

■ Conﬁgurable register supporting DDR2 Registered DIMM applications

■ Higher output drive strength version of SSTU32866 optimized for high-capacitive load

nets

■ Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

■ Controlled output impedance drivers enable optimal signal integrity and speed

■ Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation

delay; 2.0 ns max. mass-switching)

■ Supports up to 450 MHz clock frequency of operation

■ Optimized pinout for high-density DDR2 module design

■ Chip-selects minimize power consumption by gating data outputs from changing state

■ Supports SSTL_18 data inputs

■ Checks parity on the DIMM-independent data inputs

■ Partial parity output and input allows cascading of two SSTUH32866s for correct parity

error processing

■ Differential clock (CK and CK) inputs

12 3 4 5 6 7...28

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与SSTUH32866EC/G相关器件

型号	品牌	获取价格	描述	数据表
SST-ULD-S1	DOMINANT	获取价格	SpiceLED InGaN S-Spice
SST-ULD-S2	DOMINANT	获取价格	SpiceLED InGaN S-Spice
SST-ULD-ST1-1	DOMINANT	获取价格	SpiceLED InGaN S-Spice
SST-ULD-T1	DOMINANT	获取价格	SpiceLED InGaN S-Spice
SSTUM32865	NXP	获取价格	1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications
SSTUM32865EG	NXP	获取价格	1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications
SSTUM32865ES	NXP	获取价格	1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications
SSTUM32865ET	NXP	获取价格	1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications
SSTUM32865ET/G	NXP	获取价格	IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160, 9 X 13 MM, 0.70
SSTUM32865ET/G,518	NXP	获取价格	SSTUM32865 - 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applicati

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