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SSTUG32868ETS

更新时间： 2024-11-02 06:14:23

品牌	Logo	应用领域
恩智浦 - NXP		双倍数据速率
页数	文件大小	规格书
29页	167K
描述
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications

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SSTUG32868ETS 数据手册

SSTUG32868

1.8 V 28-bit 1 : 2 conﬁgurable registered buffer with parity for

DDR2-1G RDIMM applications

Rev. 01 — 23 April 2007

Product data sheet

1. General description

The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register speciﬁcally designed for use on two rank

by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It

is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the

functionality of the normally required two registers in a single package, thereby freeing up

board real-estate and facilitating routing to accommodate high-density Dual In-line

Memory Module (DIMM) designs.

The SSTUG32868 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain QERR pin (active LOW).

It further offers added features over the JEDEC standard register in that it is permanently

conﬁgured for high output drive strength. This allows use in high density designs with

heavier than normal net loading conditions. Furthermore, the SSTUG32868 features two

additional chip select inputs, which allow more versatile enabling and disabling in densely

populated memory modules. Both added features (drive strength and chip selects) are

fully backward compatible to the JEDEC standard register. Finally, the SSTUG32868 is

optimized for the fastest propagation delay in the SSTU family of registers.

The SSTUG32868 is packaged in a 176-ball, 8 × 22 grid, 0.65 mm ball pitch, thin proﬁle

ﬁne-pitch ball grid array (TFBGA) package, which (while requiring a minimum

6 mm × 15 mm of board space) allows for adequate signal routing and escape using

conventional card technology.

2. Features

I 28-bit data register supporting DDR2

I Fully compliant to JEDEC standard for SSTUB32868

I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2 × SSTUA32864 or 2 × SSTUA32866)

I Parity checking function across 22 input data bits

I Parity out signal

I Controlled multi-impedance output impedance drivers enable optimal signal integrity

and speed

I Meets or exceeds SSTUB32868 JEDEC standard speed performance

I Supports up to 450 MHz clock frequency of operation

I Permanently conﬁgured for high output drive

I Optimized pinout for high-density DDR2 module design

I Chip-selects minimize power consumption by gating data outputs from changing state

12 3 4 5 6 7...29

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与SSTUG32868ETS相关器件

型号	品牌	获取价格	描述	数据表
SSTUG32868G	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUH32864	NXP	获取价格	1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications
SSTUH32864EC	NXP	获取价格	1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications
SSTUH32864EC,518	NXP	获取价格	SSTUH32864 - 1.8 V high output drive configurable registered buffer for DDR2 RDIMM applica
SSTUH32864EC,551	NXP	获取价格	SSTUH32864 - 1.8 V high output drive configurable registered buffer for DDR2 RDIMM applica
SSTUH32864EC,557	NXP	获取价格	SSTUH32864 - 1.8 V high output drive configurable registered buffer for DDR2 RDIMM applica
SSTUH32864EC/G	NXP	获取价格	1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications
SSTUH32864EC/G,551	NXP	获取价格	SSTUH32864 - 1.8 V high output drive configurable registered buffer for DDR2 RDIMM applica
SSTUH32864EC/G,557	NXP	获取价格	SSTUH32864EC
SSTUH32865	NXP	获取价格	1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applicatio

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