Datasheet > SSTUG32866EC/G

SSTUG32866EC/G

更新时间： 2024-11-02 06:14:23

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
28页	151K
描述
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

SSTUG32866EC/G 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LFBGA,
针数：	96	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.82
系列：	32866	JESD-30 代码：	R-PBGA-B96
长度：	13.5 mm	逻辑集成电路类型：	D FLIP-FLOP
湿度敏感等级：	2	位数：	25
功能数量：	1	端子数量：	96
最高工作温度：	70 °C	最低工作温度：
输出特性：	OPEN-DRAIN	输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	1.5 ns
认证状态：	Not Qualified	座面最大高度：	1.5 mm
最大供电电压 (Vsup)：	2 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
触发器类型：	POSITIVE EDGE	宽度：	5.5 mm
最小 fmax：	550 MHz	Base Number Matches：	1

SSTUG32866EC/G 数据手册

SSTUG32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer

with parity for DDR2-1G RDIMM applications

Rev. 01 — 29 June 2007

Product data sheet

1. General description

The SSTUG32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2

memory modules requiring a parity checking function. It is deﬁned in accordance with the

JEDEC standard for the SSTUG32866 registered buffer. The register is conﬁgurable

(using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in

the latter conﬁguration can be designated as Register A or Register B on the DIMM.

The SSTUG32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is deﬁned as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

The SSTUG32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA

package (13.5 mm × 5.5 mm).

2. Features

I Conﬁgurable register supporting DDR2 up to 800 MT/s Registered DIMM applications

I Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

I Controlled output impedance drivers enable optimal signal integrity and speed

I Meets or exceeds SSTUG32866 JEDEC standard speed performance

I Supports up to 550 MHz clock frequency of operation

I Optimized pinout for high-density DDR2 module design

I Chip-selects minimize power consumption by gating data outputs from changing state

I Supports SSTL_18 data inputs

I Checks parity on the DIMM-independent data inputs

I Partial parity output and input allows cascading of two SSTUG32866s for correct parity

error processing

I Differential clock (CK and CK) inputs

I Supports LVCMOS switching levels on the control and RESET inputs

I Single 1.8 V supply operation (1.7 V to 2.0 V)

I Available in 96-ball, 13.5 mm × 5.5 mm, 0.8 mm ball pitch LFBGA package

3. Applications

I 400 MT/s to 800 MT/s and higher DDR2 registered DIMMs desiring parity checking

functionality

12 3 4 5 6 7...28

中文翻译

下载PDF

与SSTUG32866EC/G相关器件

型号	品牌	获取价格	描述	数据表
SSTUG32866EC/G,518	NXP	获取价格	SSTUG32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUG32866EC/S	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/S,518	NXP	获取价格	SSTUG32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUG32868	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32868ET	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32868ET/G,518	NXP	获取价格	SSTUG32868 - 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDI
SSTUG32868ET/S,518	NXP	获取价格	SSTUG32868 - 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDI
SSTUG32868ETS	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32868G	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUH32864	NXP	获取价格	1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications

与SSTUG32866EC/G相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

5
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

2
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

23
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

24

产品中心

服务支持

精选活动

关于我们

帮助中心

SSTUG32866EC/G

SSTUG32866EC/G 技术参数

SSTUG32866EC/G 数据手册

与SSTUG32866EC/G相关器件

与SSTUG32866EC/G相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SSTUG32866EC/G

SSTUG32866EC/G 技术参数

SSTUG32866EC/G 数据手册

与SSTUG32866EC/G相关器件

与SSTUG32866EC/G相关文章

您还可以找

您在本页遇到什么问题？