Datasheet > SSTUB32872AHMLF

SSTUB32872AHMLF

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	209K
描述
CABGA-96, Tray

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中文翻译

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数据手册

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SSTUB32872AHMLF 数据手册

ICSSSTUB32872A

Integrated

Circuit

Advance Information

Systems,Inc.

28-Bit Registered Buffer for DDR2

Pin Configuration

Recommended Application:

•

DDR2 Memory Modules

•

Provides complete DDR DIMM solution with

ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A

•

Optimized for DDR2 400/533/667 JEDEC 4 Rank

VLP DIMMS

Product Features:

•

28-bit 1:1 registered buffer with parity check

functionality

Supports SSTL_18 JEDEC specification on data

inputs and outputs

Supports LVCMOS switching levels on RESET input

50% more dynamic driver strength than standard

SSTU32864

Low voltage operation

V_DD= 1.7V to 1.9V

Available in 96 BGA package

•

96 Ball BGA

(Top View)

FunctionalityTruthTable

Inputs

Outputs

QCS

Dn,

DODTn,

DCKEn

QODT,

QCKE

RESET

DCS0

DCS1

↓

↑

↓

L or H

↓

↑

L or H

↑

Q₀

↓

↑

L or H

↑

Q₀

L or H

↓

↑

Q₀

L or H

Q₀

↓

↑

L or H

Q₀

X or

floating

X or

floating

X or

floating

X or

floating

X or

floating

1222F—3/13/07

ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.

ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

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