Datasheet > SSTUG32865

SSTUG32865

更新时间： 2024-11-02 09:03:39

品牌	Logo	应用领域
恩智浦 - NXP		双倍数据速率
页数	文件大小	规格书
28页	154K
描述
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-1G RDIMM applications

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SSTUG32865 数据手册

SSTUG32865

1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-1G

RDIMM applications

Rev. 01 — 16 August 2007

Product data sheet

1. General description

The SSTUG32865 is a 1.8 V 28-bit 1 : 2 register speciﬁcally designed for use on two rank

by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It

is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the

functionality of the normally required two registers in a single package, thereby freeing up

board real-estate and facilitating routing to accommodate high-density Dual In-line

Memory Module (DIMM) designs.

The SSTUG32865 also integrates a parity function, which accepts a parity bit from the

memory controller, compares it with the data received on the D-inputs and indicates

whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

It further offers added features over the JEDEC standard register in that it can be

conﬁgured for normal or high output drive strength, simply by tying input pin SELDR either

HIGH of LOW as needed. This allows use in different module designs varying from low to

high density designs by picking the appropriate drive strength to match net loading

conditions. Furthermore, the SSTUG32865 features two additional chip select inputs,

which allow more versatile enabling and disabling in densely populated memory modules.

Both added features (drive strength and chip selects) are fully backward compatible to the

JEDEC standard register.

The SSTUG32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin proﬁle

ﬁne-pitch ball grid array (TFBGA) package, which, while requiring a minimum

9 mm × 13 mm of board space, allows for adequate signal routing and escape using

conventional card technology.

2. Features

I 28-bit data register supporting DDR2

I Fully compliant to JEDEC standard for SSTUB32865

I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two

JEDEC-standard DDR2 registers (that is, 2 × SSTUB32864 or 2 × SSTUB32866)

I Parity checking function across 22 input data bits

I Parity out signal

I Controlled multi-impedance output impedance drivers enable optimal signal integrity

and speed

I Exceeds SSTUB32865 JEDEC standard speed performance

I Supports up to 550 MHz clock frequency of operation

I Programmable for normal or high output drive

I Optimized pinout for high-density DDR2 module design

12 3 4 5 6 7...28

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与SSTUG32865相关器件

型号	品牌	获取价格	描述	数据表
SSTUG32865ET/G	NXP	获取价格	IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160, 9 X 13 MM, 0.70
SSTUG32865ET/G,518	NXP	获取价格	SSTUG32865 - 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32865ET/S	NXP	获取价格	IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160, 9 X 13 MM, 0.70
SSTUG32866	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/G	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/G,518	NXP	获取价格	SSTUG32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUG32866EC/S	NXP	获取价格	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
SSTUG32866EC/S,518	NXP	获取价格	SSTUG32866 - 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity
SSTUG32868	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio
SSTUG32868ET	NXP	获取价格	1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applicatio

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