SN75LVDS81
FLATLINK TRANSMITTER
SLLS258B – NOVEMBER 1996 – REVISED MAY 1999
DGG PACKAGE
(TOP VIEW)
28:4 Data Channel Compression at up to
227.5 Million Bytes per Second Throughput
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
V
D4
1
56
55
54
53
52
51
50
49
48
47
46
CC
D5
D3
2
D6
D7
D2
3
28 Data Channels and Clock In Low-Voltage
TTL
GND
D1
4
GND
D8
5
D0
6
4 Data Channels and Clock-Out
Low-Voltage Differential
D9
D27
LVDSGND
Y0M
Y0P
Y1M
7
D10
8
Operates From a Single 3.3-V Supply With
250 mW (Typ)
V
9
CC
D11
D12
10
11
5-V Tolerant Data Inputs
Falling Clock-Edge-Triggered Inputs
D13 12
GND 13
D14 14
45 Y1P
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
44 LVDSV
CC
43 LVDSGND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D15
D16
NC
Y2M
Consumes Less Than 1 mW When Disabled
Y2P
Wide Phase-Lock Input Frequency
Range . . . 31 MHz to 68 MHz
CLKOUTM
CLKOUTP
Y3M
D17
D18
D19
GND
D20
D21
D22
D23
No External Components Required for PLL
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
Y3P
LVDSGND
PLLGND
Improved Replacement for the National
DS90C581
PLLV
CC
PLLGND
SHTDN
CLKIN
D26
description
V
CC
The SN75LVDS81 FlatLink transmitter contains
four 7-bit parallel-load serial-out shift registers, a
7× clock synthesizer, and five low-voltage
differential-signaling (LVDS) line drivers in a
single integrated circuit. These functions allow
D24
D25
GND
NC – Not Connected
28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for
receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS81 can also be used in 21-bit links
with the SN75LVDS86 receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the falling edge of the input
clock signal (CLKIN) The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data
registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output
to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS81 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The
only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock
and shut off the LVDS output drivers for lower power consumption. A low-level on SHTDN clears all internal
registers to a low level.
The SN75LVDS81 is characterized for operation over free-air temperature ranges of 0 C to 70 C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a registered trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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